• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1387-1390
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• 2003

The superscalar architecture shows limit in performance improvement recently. While, SMT(Simultaneous Multi-Threading) architecture is receiving remark. The purpose of SMT architecture is to improve the performance of superscalar microprocessors by executing multi threads at the same time. In this paper, a load/store unit(LSU) suitable for ARM-compatible SMT microprocessors is presented. This LSU supports load instructions and store instructions of ARM ISA. This LSU keeps away the degradation of SMT by cache miss.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1383-1386
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• 2003

In this paper, an ALU for Simultaneous Multi-Threading (SMT) microprocessors is designed. The SMT architecture improves notably performance and utilization of processes compared with conventional superscalar architectures by executing instructions from multiple threads at the same time. This ALU adopts data bypassing method to process multi-threads. And it can flush instructions in the same thread that generate exceptions such as branch misprediction. interrupt etc, performance of SMT microprocessors with data bypassing and exception handler can be improved.

• International Journal of Aeronautical and Space Sciences
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• v.14 no.2
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• pp.112-121
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• 2013

An approach for composing a performance optimized computational code is suggested for the latest microprocessors. The concept of the code optimization, termed localization, is maximizing the utilization of the second level cache that is common to all the latest computer systems, and minimizing the access to system main memory. In this study, the localized optimization of the LU-SGS (Lower-Upper Symmetric Gauss-Seidel) code for the solution of fluid dynamic equations was carried out in three different levels and tested for several different microprocessor architectures widely used these days. The test results of localized optimization showed a remarkable performance gain of more than two times faster solution than the baseline algorithm for producing exactly the same solution on the same computer system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.220-228
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• 2001

Simulation of an instruction set is essential to design and optimize new microprocessors, and to develop application programs. Though many simulation tools are widely used, their low-level description and simulation make users construct simulators difficult and spend a lot of time for simulation. We developed an automatic generator of instruction set simulators that perform register-transfer-level simulation. This automatic generator might be adaptable so as to be suitable for new modification or different conditions in designing microprocessors. In this paper, we describe a structure of automatic generation system and an implementation details.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.232-235
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• 1999

In this paper, we present a coprocessor that can operate with ARM microprocessors. The coprocessor supports IEEE 754 standard single- and double-precision binary floating point arithmetic operations. The design objective is to achieve minimum-area, low-power and acceleration of processing power of ARM microprocessors. The instruction set is compatible with ARM7500FE. The coprocessor is written in verilog HDL and synthesized by the SYNOPSYS Design Compiler. The gate count is 38,115 and critical path delay is 9.52ns.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.931-934
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• 1999

For applications in multimedia to which genuine RISC microprocessors are not suitably applicable, a new generation of fast and flexible microprocessors is required. In this paper, as a technique of integrating DSP functionality in a general RISC processor, a RISC that can execute DSP extension instructions is developed to improve the performance of multimedia application execution. This processor can execute DSP instructions in parallel with the execution of ALU instructions for efficient and fast execution. In addition, the execution ability of integer instructions is improved by enhancing the RISC core itself.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1684-1685
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• 2007

Development of software for microprocessors is one of the areas where UML can be used. There are many UML tools which is capable of generating source code for microprocessors. In this paper, a part of CANopen protocol is implemented using UML and the source code generated by a UML tool is tested.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.5
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• pp.815-824
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• 2013

Traditionally embedded microprocessors is considered as a device for low- and simple-computations because of its limited computing power and constrained resources. However high-end embedded devices have been developed and many applications are getting feasible in the embedded devices. To provide secure and robust service environments, security on embedded devices are in order. Recently many research results on embedded devices have been proposed. In this paper, we explore various cryptography implementation results on representative 8-, 16- and 32-bit embedded processors including AVR, MSP and ARM. This report would be helpful for following researchers who are interested in cryptography implementation techniques on resource constrained devices.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.5
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• pp.36-42
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• 1980

In this study, multi-microprocessors system in which slave microprocessor is conrlected with master microprocessor bus through the DMA controller is designed by the use of four 8085 CPU. A high degree of processing efficiency could be obtained by making this system work parallel processing. The result of measuring relat ions bet ween working microproressor and system throughput was 70-80 percents lower than ideal value Master microprocessor takes charge of resource allocation and scheduling, common memory assigns communication between microprocessors and a store of common data. The met hod of detecting Pa rallelism from source Program composed by series is also suggested.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.2051-2054
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• 2004

This paper proposes a more accurate task level energy measurement technique for high speed microprocessors. The technique is based on the relationship of the amount of current consumed by the microprocessor and the pulse width of the power supply controller chip, employed in the synchronous buck DC-DC converter in the microprocessor's power supply. The accuracy of the measurement is accomplished by measuring variation in pulse width in each power supply cycle. The major advantage of this technique is that its accuracy does not depend on the operating frequency of the microprocessor. To prove the proposed technique, we implemented the measurement unit of the microprocessor energy meter using an FPGA chip operating at 50 MHz. Both static and dynamic load measurement are tested in order to obtain some behaviours. Moreover, various commercially available mainboards which employ synchronous buck regulators at 200 KHz switching frequency, were measured. The results agree with previous works with better accuracy at higher operating frequency.