• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.2
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• pp.28-33
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• 1976

In recent years, Microprocessor have the use of extended wide fiexd because of obtainable to low price. Design of computer system be easy to do by this microprocessor apply validly. This Papers: NOVA Emulator designed by use of MMI-6701. As a result of this studies, quantity of IC changed with about a third part by NOVA exchanged with Microprocessor. Micro Instruction of PROM consist of 32bit that designed Instruction Format of four kinds.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.333-336
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• 2002

This paper purpose design and implementation of system bus for the effective interconnection between peripheral device and 32-bit microprocessor. The designed system bus support general bus protocol. Also, it is optimized for 32-bit microprocessor. It is divided into two system. high performance system bus and Peripheral system bus.

• Journal of the Korean Society for Precision Engineering
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• v.1 no.2
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• pp.69-74
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• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2910 "bit-slice" microprocessor chips and 0.5K ROMs of microprogram memory. The system design is an instruction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolatioon speed of (max) 250K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software of the interpolator efficently. In addi- tion to hardware and software design, experimental results are pressented.ressented.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.68-74
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• 2002

In this paper, a pre-layout design approach for high-speed microprocessor is proposed. For multilayer PCB stark up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system. The system model includes VRM, decoupling capacitors, multiple power and ground planes for core voltage, vias, as well as microprocessor. Finally, the simulation results are verified by measurements data.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.2
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• pp.62-69
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• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2900 "bit-slice" microprocessor chips and 0.5K ROMs of 36-bit microprogram memory. The system design is an instuction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolation speed of 250 K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software, and experimental results are presented.presented.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.486-490
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• 2004

Programmable logic controller (PLC) is widely used in manufacturing system or process control. This paper presents the design of a 32-bit microprocessor for a sequence control using an Application Specification Integrated Circuit (ASIC). The 32-bit microprocessor was designed by a VHDL with top down method; the program memory was separated from the data memory for high speed execution of 274 specified sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. And in order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32-bits. And the real time debugging as single step run, break point run was implemented. Pulse instruction, step controller, master controllers, BIN and BCD type arithmetic instructions, barrel shit instructions were implemented for many used in PLC system. The designed microprocessor was synthesized by the S1L50000 series which contains 70,000 gates with 0.65um technology of SEIKO EPSON. Finally, the benchmark was performed to show that designed 32-bit microprocessor has better performance than Q4A PLC of Mitsubishi Corporation.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.163-167
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• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.193-196
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• 2001

In this paper we designed CAMC-SP, the microprocessor embedded 2-axis motor control chip which controls a precise pulse motor by generating the pulse needed to control step motor, DC servo and AC servo motor. This design enables to decrease costs and to minimize a size. First we designed risc type 8-bit microprocessor compatible with PIC16C84, second we designed pulse motor controller. CAMC-SP is integrated of those two block. We designed CAMC-SP by VHDL and we testified to the Performance of it by performing functional simulation.

• The Journal of Information Technology
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• v.9 no.1
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• pp.33-39
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• 2006

This study is for the contents of development to the hardware system and software driving algorithm to implement the frequency band of about 7KHz los pass digital filter which has the cut-off frequency of 392Hz by interfacing of a microprocessor with its peripheral analog-to-digital converter chip and digital-to-analog converter chip. The simplicity of digital filter design without difficulty and the implementation of programmed digital filter can be realized by providing the interfacing method to implement the law pass digital filter for the biological signals and the realization method of computer algorithm by a microprocessor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.2
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• pp.292-300
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• 1987

This paper, realizes the design of the sequential controller of a reinforced warehousing-delivery and unmanned transportation system for automated warehouse system. The system is composed of ware housing delivery adn transportation system using two unmanned vehicles with hierachical structure. It is described by GRAFCET and realized by programmed logic with microprocessor. Being described by GRAFCET, the system is able to divide it into subsystems and to synchronize them. Defining the concept of program module, one can easily program the system with the microprocessor instruction language.