• Korean Journal of Metals and Materials
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• v.48 no.6
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.2 s.43
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• pp.23-33
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• 2007

The growing environmental regulation governs the use of lead by RoHS, WEEE, and then. The electronic industry is moving to replace Pb-bearing solder with Pb-free solder. To use the Pb-free solder, microelectronic industry needs consequently the new reliability appraisal such as the packaging for high temperature process, various mechanical change caused by new solder, and the development of Pb-free sloder for long life of product. The evaluation of solder bar and mechanical properties of joint were performed compared with international standard, and new appraisal standard was established. The solderability and spread ability of Sn-0.7Cu solder material showed up to the standard. Shear test of solder joint using by the solder resulted that the shear strengths after thermal shock or after aging were not much lower than the shear strength of as-soldered and that they were also up to the standard.

• Applied Chemistry for Engineering
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• v.8 no.3
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• pp.533-542
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• 1997

Due to the trends of faster and denser circuit design, dielectric properties of packaging materials for semiconductor will give a greater influence on performance and reliability. Also as chip becomes more densified, thermal dissipation becomes a critical reliability issue. Consequently, four important properties for manufacturing semiconductor packaging materials are low values of dielectric constant, high values of thermal conductivity, relatively low values of thermal expansion coefficient and low cost. Thus, in this study, to achieve increased performance of EMC, crystalline silica was selected as the filler for epoxy matrix. As a result, when the volume percent of crystal silica was 60~70%, good properties as packaging materials for semiconductor were achieved. In addition, overall molding condition of EMC in this experiment was established.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.84-87
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• 2003

Since Pb-free solder alloys have been used extensively in microelectronic packaging industry, the interaction between UBM (Under Bump Metallurgy) and solder is a critical issue because IMC (Intermetallic Compound) at the interface is critical for the adhesion of mechanical and the electrical contact for flip chip bonding. IMC growth must be fast during the reflow process to form stable IMC. Too fast IMC growth, however, is undesirable because it causes the dewetting of UBM and the unstable mechanical stability of thick IMC. UP to now. Ni and Cu are the most popular UBMs because electroplating is lower cost process than thin film deposition in vacuum for Al/Ni(V)/Cu or phased Cr-Cu. The consumption rate and the growth rate of IMC on Ni are lower than those of Cu. In contrast, the wetting of solder bumps on Cu is better than Ni. In addition, the residual stress of Cu is lower than that of Ni. Therefore, the alloy of Cu and Ni could be used as optimum UBM with both advantages of Ni and Cu. In this paper, the interfacial reactions of Sn-3.5Ag-0.7Cu solder on Ni-xCu alloy UBMs were investigated. The UBMs of Ni-Cu alloy were made on Si wafer. Thin Cr film and Cu film were used as adhesion layer and electroplating seed layer, respectively. And then, the solderable layer, Ni-Cu alloy, was deposited on the seed layer by electroplating. The UBM consumption rate and intermetallic growth on Ni-Cu alloy were studied as a function of time and Cu contents. And the IMCs between solder and UBM were analyzed with SEM, EDS, and TEM.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.41-48
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• 1999

Silica is the most popular materials as a filler of EMC for microelectronic packaging. However, because of its low thermal conductivity, the use of silica is restricted to parts requiring high thermal dissipation. The superior fluidity of EMC can be achieved with a combination of filler size distribution. In this study, physical properties of EMC filled with the crystalline silica(13$\mu\textrm{m}$) which have high fluidity and low cost and the AlN(2 $\mu\textrm{m}$) which have high thermal conductivity and low coefficient of thermal expansion were evaluated by changing the AlN/silica ratios. As a result of the evaluation of physical properties of EMC, the optimum mixing ratio of AlN/crystalline silica was 0.3/0.7. In this condition, binary mixture(AlN/crystalline silica) filled EMC showed superior properties, i.e., in the thermal conductivity, CTE, dielectric constant, flexural strength, and thermal shock resistance without reduction of fluidity.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.11-18
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• 2022

Recently, as flexible electronic device-related technologies have received worldwide attention, the development of wiring and bonding technologies using liquid metals is required in order to improve problems such as formability in the manufacturing process of flexible devices and performance and durability in the bending state. In response to these needs, various studies are being conducted to use gallium and gallium-based alloys (eutectic Ga-In and eutectic Ga-In-Sn, etc.) liquid metals, with low viscosity and excellent electrical conductivity without toxicity, as low-temperature bonding materials. In this paper, the latest research trends of low-temperature bonding technology using gallium and gallium-based alloys are summarized and introduced. These technologies are expected to become important base technologies for practical use in the fields of manufacturing flexible electronic devices and low-temperature bonding in microelectronic packages in the future.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.2
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• pp.79-84
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• 2016

A flexible electronic device deformed by external force causes the failure of a semiconductor die. Even without failure, the repeated elastic deformation changes carrier mobility in the channel and increases resistivity in the interconnection, which causes malfunction of the integrated circuits. Therefore it is desirable that a semiconductor die be placed on a neutral line where the mechanical stress is zero. In the present study, we investigated the effects of design factors on the position of neutral line by finite element analysis (FEA), and expected the possible failure behavior in a flexible face-down packaging system assuming flip-chip bonding of a silicon die. The thickness and material of the flexible substrate and the thickness of a silicon die were considered as design factors. The thickness of a flexible substrate was the most important factor for controlling the position of the neutral line. A three-dimensional FEA result showed that the von Mises stress higher than yield stress would be applied to copper bumps between a silicon die and a flexible substrate. Finally, we suggested a designing strategy for reducing the stress of a silicon die and copper bumps of a flexible face-down packaging system.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.3
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• pp.43-55
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• 2003

As the development of If industries and their electronic device manufacturing technology have been accelerated recently, the request for electronic devices with small size, light weight, and high performance has been inducing that electronic package and substrate (PCB) companies have to develop substrates with low cost, high dense I/O, excellent thermal properties and electrical properties. Therefore, world-wide chip makers have been setting their own severe reliability standards and requiring their suppliers to keep specification and to develop green, high frequency and high-performing substrates. Because properties of substrates are dependent mainly on their constituent materials, the application of them showing superior properties is expected to satisfy the customer's requirement. Therefore, substrate companies should ensure the superiority of materials and assure their competitive capability of substrates by analyzing the latest trends of technology and properties of the materials.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1946-1949
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• 1996

We have performed silicon-to-silicon anodic bonding using glass layer deposited by electron beam evaporation. Wafers can be bonded at $135^{\circ}C$ with an applied voltage of $35V_{DC}$, which enables application of this technique to the vacuum packaging of microelectronic devices, because its bonding temperature and voltage are low. From the experimental results, we have found that the evaporated glass layer more than $1\;{\mu}$ m thick was suitable for anodic bonding. The role of sodium ions for anodic bonding was also investigated by theoretical bonding mechanism and experimental inspection.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.124-129
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• 1989

The cordierite is of great interest for microelectronic packaging. Its main advantages are low dielectric constant and low thermal expansion. The cordierite precursor obtained by sol-gel synthesis whose sintering temperature is about $900^{circ}C$ is an amorphous and cristal white powder. Green and fired cordierite samples were studied by XPS for microscopic properties. At the surface the results of XPS show forte diminution of Mg in comparison with its value at volume and the deficit of Mg compensates by augmentation of Al and Si. $pi$-cordierite phase is present near the surface $<100{\AA}$ and small quantities of magnesium aluminate ($MgAl_2O_4) is present in the bulk. Sintering of the green cordierite introduces no chemical modification at the surface.