• Journal of Welding and Joining
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• 제24권2호
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• pp.34-41
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• 2006

• Transactions on Electrical and Electronic Materials
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• 제10권3호
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• pp.71-74
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• 2009

Electroplated Cu is a cost efficient metallization method in microelectronic packaging applications. Typically in 3-D chip staking technology, utilizing through silicon via (TSV), electroplated Cu metallization is inevitable for the throughput as well as reducing the cost of ownership (COO).To achieve a comparable film quality to sputtering or CVD, a pre-cleaning process as well as plating process is crucial. In this research, atmospheric plasma is employed to reduce the usage of chemicals, such as trichloroethylene (TCE) and sodium hydroxide (NaHO), by substituting the chemical assisted organic cleaning process with plasma surface treatment for Cu electroplating. By employing atmospheric plasma treatment, marginally acceptable electroplating and cleaning results are achieved without the use of hazardous chemicals. The experimental results show that the substitution of the chemical process with plasma treatment is plausible from an environmentally friendly aspect. In addition, plasma treatment on immersion Sn/Cu was also performed to find out the solderability of plasma treated Sn/Cu for practical industrial applications.

• 마이크로전자및패키징학회지
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• 제6권1호
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• pp.11-21
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• 1999

For microelectronic packaging application, the crystallizable glass powder in CaO-$A1_2O_3-SiO_2-B_2O_3$system was mixed with various amounts of alumina inclusions (\approx 4 $\mu \textrm{m}$), and its sintering behavior, crystallization behavior, and dielectric constant were examined in terms of vol% of alumina and the reaction between the alumina and the glass. Sintering of the CASB glass powder alone at $900^{\circ}C$ resulted in full densification (99.5%). Sintering of alumina-filled composite at $900^{\circ}C$ also resulted in a substantial denslfication higher than 97% of theoretical density, In this case, the maximum volume percent of alumina should be less than 40%. XRD analysis revealed that there was a partial dissolution of alumina into the glass. This alumina dissolution, however, did not show the particle growth and shape accommodation. Therefore, the sintering of both the pure glans and the alumina-filled composite was mainly achieved by the viscous flow and the redistribution of the glass. Alumina dissolution accelerated the crystallization initiation time at $1000^{\circ}C$ and hindered the densification of the glass. Dielectric constants of both the alumina-filled glass and the glass-ceramic composites were increased with increasing alumina content and followed rule of mixture. In case of the glass-ceramic matrix composites showed relatively lower dielectric constant than the glass matrix composite. Furthermore, as alumina content increased, crystallization behavior of the glass was changed due to the reaction between the glass and the alumina. As alumina reacted with the glass matrix, the major crystallized phase was shifted from wollastonite to gehlenite. In this system, alumina dissolution strongly depended on the particle size: When the particle size of alumina was increased to 15 $\mu\textrm{m}$, no sign of dissolution was observed and the major crystallized phase was wollastonite.

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.280-288
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• 2016

Microelectronic product consumers may already be expecting another paradigm shift with smarter phones over smart phones, but the current status of microelectronic manufacturing engineering education (MMEE) in universities hardly makes up the pace for such a fast moving technology paradigm shift. The purpose of MMEE is to educate four-year university graduates to work in the microelectronics industry with up-to-date knowledge and self-motivation. In this paper, we present a comprehensive curriculum for a four-year university degree program in the area of microelectronics manufacturing. Three hands-on experienced-based courses are proposed, along with a methodology for undergraduate students to acquire hands-on experience, towards integrated circuits (ICs) design, fabrication and packaging, are presented in consideration of manufacturing engineering education. Semiconductor device and circuit design course for junior level is designed to cover how designed circuits progress to micro-fabrication by practicing full customization of the layout of digital circuits. Hands-on experienced-based semiconductor fabrication courses are composed to enhance students’ motivation to participate in self-motivated semiconductor fab activities by performing a series of collaborations. Finally, the Microelectronics Packaging course provides greater possibilities of mastered skillsets in the area of microelectronics manufacturing with the fabrication of printed circuit boards (PCBs) and board level assembly for microprocessor applications. The evaluation of the presented comprehensive curriculum was performed with a students’ survey. All the students responded with “Strongly Agree” or “Agree” for the manufacturing related courses. Through the development and application of the presented curriculum for the past six years, we are convinced that students’ confidence in obtaining their desired jobs or choosing higher degrees in the area of microelectronics manufacturing was increased. We confirmed that the hypothesis on the inclusion of handson experience-based courses for MMEE is beneficial to enhancing the motivation for learning.

• 한국분말재료학회지
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• 제13권5호
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• pp.321-326
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• 2006

Electronic packaging involves interconnecting, powering, protecting, and cooling of semiconductor circuits fur the use in a variety of microelectronic applications. For microelectronic circuits, the main type of failure is thermal fatigue, owing to the different thermal expansion coefficients of semiconductor chips and packaging materials. Therefore, the search for matched coefficients of thermal expansion (CTE) of packaging materials in combination with a high thermal conductivity is the main task for developments of heat sink materials electronics, and good mechanical properties are also required. The aim of this work is to develop copper matrix composites reinforced with carbon nanofibers. The advantages of carbon nanofibers, especially the good thermal conductivity, are utlized to obtain a composite material having a thermal conductivity higher than 400 W/mK. The main challenge is to obtain a homogeneous dispersion of carbon nanofibers in copper. In this paper, a technology for obtaining a homogeneous mixture of copper and nanofibers will be presented and the microstructure and properties of consolidated samples will be discussed. In order to improve the bonding strength between copper and nanofibers, different alloying elements were added. The microstructure and the properties will be presented and the influence of interface modification will be discussed.

• 마이크로전자및패키징학회지
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• 제19권1호
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• pp.17-24
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• 2012

Recently, flip chip interconnection has been increasingly used in microelectronic assemblies. The common Flip chip interconnection is formed by reflow of the solder bumps. Lead-Tin solders and Tin-based solders are most widely used for the solder bump materials. However, the flip chip interconnection using these solder materials cannot be applied to temperature-sensitive components since solder reflow is performed at relatively high temperature. Therefore the development of low temperature bonding technologies is required in these applications. A few bonding techniques at low temperature of $150^{\circ}C$ or below have been reported. They include the reflow soldering using low melting point solder bumps, the transient liquid phase bonding by inter-diffusion between two solders, and the bonding using low temperature curable adhesive. This paper reviews various low temperature bonding methods.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.19-25
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• 2000

Dielectric polymer films produced from benzocyclobutene (BCB) formulations (CYCLOTENE＊ family resins) are known to possess many desirable properties for microelectronic applications; for example, low dielectric constant and dissipation factor, low moisture absorption, rapid curing on hot plate without reaction by-products, minimum shrinkage in curing process, and no Cu migration issues. Recently, BCB-based products for thick film applications have been developed, which exhibited excellent dissipation factor and dielectric constant well into the GHz range, 0.002 and 2.50, respectively. Derived from these properties, the applications are developed in: bumping/wafer level packaging, Ga/As chip ILD, optical waveguide, flat panel display, and lately in BCB-coated Cu foil for build-up board. In this paper, we review the relevant properties of BCB, then the application areas in bumping/wafer level packaging and BCB-coated Cu foil for build-up board.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.1004-1006
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• 1998

Mo-tip FED of 1 inch diagonal was vacuum sealed using sodalime-to-sodalime glass electrostatic bonding under $10^{-7}torr$. The bonding properties of the bonded sodalime-to sodalime structure were investigated and emission characteristic of packaged FED panel was measured.

• 한국복합재료학회:학술대회논문집
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• 한국복합재료학회 2000년도 춘계학술발표대회 논문집
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• pp.131-134
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• 2000

Increased temperature adversely affects the reliability of a device. So, package material should have high thermal diffusion, i.e., high thermal conductivity. And, there are several other physical properties of polymeric materials that are important to microelectronics packaging, some of which are a low dielectric constant, a low coefficient of thermal expansion (CTE), and a high flexural strength. In this study, to get practical maximum packing fraction of AIN (granular type) filled EMC, the properties such as the spiral flow, thermal conductivity, CTE, and water resistance of AIN-filled EMC (65-vol%) were evaluated according to the size of AIN and the filler-size distribution. Also, physical properties of AIN filled EMC above 65-vol% were evaluated according to increasing AIN content at the point of maximum packing fraction (highly loading condition). The high loading conditions of EMC were set $D_L/D_S$=12 and $X_S$=0.25 like as filler of sphere shape and the AIN filled EMC in this conditions can be obtained satisfactory fluidity up to 70-vol%. As a result, the AIN filled EMC (70-vol%) at high loading condition showed improved thermal conductivity (about 6 W/m-K), dielectric constant (2.0~3.0), CTE(less than 14 ppm/$^{\circ}C$) and water resistance. So, the AIN filled EMC (70-vol%) at high loading condition meets the requirement fur advanced microelectronic packaging materials.