• International Journal of Computer Science & Network Security
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• v.21 no.4
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• pp.264-271
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• 2021

From an information security perspective, protecting sensitive data requires utilizing algorithms which resist theoretical attacks. However, treating an algorithm in a purely mathematical fashion or in other words abstracting away from its physical (hardware or software) implementation opens the door to various real-world security threats. In the modern age of electronics, cryptanalysis attempts to reveal secret information based on cryptosystem physical properties, rather than exploiting the theoretical weaknesses in the implemented cryptographic algorithm. The correlation power attack (CPA) is a Side-Channel Analysis attack used to reveal sensitive information based on the power leakages of a device. In this paper, we present a power Hacking technique to demonstrate how a power analysis can be exploited to reveal the secret information in AES crypto-core. In the proposed case study, we explain the main techniques that can break the security of the considered crypto-core by using CPA attack. Using two cryptographic devices, FPGA and 8051 microcontrollers, the experimental attack procedure shows that the AES hardware implementation has better resistance against power attack compared to the software one. On the other hand, we remark that the efficiency of CPA attack depends statistically on the implementation and the power model used for the power prediction.

• Nuclear Engineering and Technology
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• v.53 no.4
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• pp.1167-1175
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• 2021

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration.

• Journal of Drive and Control
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• v.19 no.2
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• pp.17-26
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• 2022

Recently, automatic transmissions caused a good improvement in the shift quality of a forklift. An advanced shift control algorithm, which was based on TCU firmware, was applied with embedded control technology and microcontrollers. In the clutch-to-clutch shifting, one friction element is released and the other friction element is activated. During this process, if the release and application timings are not synchronized, an overrun or tie-up occurs and ultimately leads to a shift shock. The TCU, which measures only the speed of the forklift, inevitably applies the open-loop shift control. In this situation, the speed ratio does not change during the clutch fill. The torque phase occurs until the clutch is disengaged. In this study, an offline shift logic of the learning control was proposed. It induced a synchronous shift when the learning control progressed. During this process, the reference current trajectory of the release clutch was corrected and applied to the next upshift. We considered the results of the overrun/tie-up characteristics of the upshift performed immediately before. The vehicle test proved that the deviation in shift quality, which was caused by the difference in the mechanical characteristics of the clutch, could be improved by the learning control.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.1
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• pp.237-243
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• 2015

In this paper, we consider a cascaded type of control architecture for a multi motor-based feedback control system and propose an ADC (Analog to Digital Converter) resource allocation method to efficiently utilize the limited ADC resources. The purpose of the resource allocation method is to minimize both the motor position measurement error and the d-q current measurement error. The cascaded type of control architecture is applied in parallel to each motor to independently control the speed of a motor in the multi motor control system. All the control algorithms are implemented by software using a single microcontroller without using additional microcontrollers. It is illustrated by experiments that the speed and the torque of each motor are controlled precisely by the proposed control architecture with the efficient ADC allocation method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.63-71
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• 2002

This paper suggests a 8-bit RISC microcontroller, which has a 4-stage pipeline architecture. Many low-power design techniques that have been proposed by previous works are adopted into it. The proposed microcontroller consumes only 600㎼ per MIPS for 0.6 ${\mu}{\textrm}{m}$ CMOS process and even lower power of 70㎼ per MIPS for 0.25${\mu}{\textrm}{m}$ process. The RTL level design of this microcontroller is carried out using VHDL. The functional verification is thoroughly done at the gate level using 0.6${\mu}{\textrm}{m}$/0.25${\mu}{\textrm}{m}$ CMOS IDEC standard cell library. This microcontroller contains 7000 NAND gates on a 0.36$\textrm{mm}^2$ die using 0.25${\mu}{\textrm}{m}$ process. Finally the comparison of power consumption with other conventional microcontrollers is provided.

• Transactions on Control, Automation and Systems Engineering
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• v.3 no.3
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• pp.181-189
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• 2001

The software components of embedded control systems get extremely complex as they are designed into distributed systems get extremely complex as they are designed into distributed systems consisting of a large number of inexpensive microcontrollers interconnected by low-bandwidth real-time networks such as the controller area network (CAN). While recently emerging middleware technologies such as CORBA and DCOM address the complexity of distributed programming, they cannot be directly applied to distributed control system design due to their excessive resource demand and inadequate communication models. In this paper, we propose a CORBA-based middleware design for CAN-based distributed embedded control systems. Our design goal is to minimize its resource need and make it support group communication without losing the IDL (interface definition language) level compliance to the OMG standards. To achieve this, we develop a transport protocol on the CAN and a group communication scheme based on the well-known publisher/subscriber model. The protocol effectively realizes subject-based addressing and supports anonymous publisher/subscriber communication. We also customize the method invocation and message passing protocol, referred to as the general inter-ORB protocol (GIOP), of CORBA so that CORBA method invocations are efficiently serviced on a low-bandwidth network such as the CAN. This customization includes packed data encoding and variable-length integer encoding for compact representation of IDL data types. We have implemented our CORBA-based middleware on the mArx real-time operating system we have developed at Seoul National University. Our experiments clearly demonstrate that it is feasible to use CORBA in developing distributed embedded control systems possessing severe resource limitations. Our design clearly demonstrates that it is feasible to use a CORBA-based middleware in developing distributed embedded systems on real-time networks possessing severe resource limitations.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.414-420
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• 2005

The ShortStack Micro Server enables any product that contains a microcontroller or microprocessor to quickly and inexpensively become a networked, Internet-accessible device. The ShortStack Micro Server provides a simple way to add LonWorks networking to new or existing smart devices. . It implements the LonTalk protocol and provides the physical interface with the LonWorks communication. The ShortStack host processor can be an 8, 16, or 32-bit microprocessor or microcontrollers. The ShortStack API and driver typically require about 4kbytes of program memory on the host processor and less than 200 bytes of RAM. The interface between host processor and the ShortStack Micro Server may be a Serial Communication Interface (SCI). The LonWorks control module with a high performance is developed, which is composed of the 8 bit PIC Microprocessor for host processor and the smart neuron chip for the ShortStack Micro Server. This intelligent control board is verified as proceeding the various function tests from experimental system with an boost pump and inverter driving systems. It is also confirmed that the developed control module provides stably 0-10VDC linear signal to the input signal of inverter driving system for varying the induction motor speed. Thus, the experimental results show that the fabricating intelligent board carried out very well the various functions in the wide operating ranges of boost pump system. This developed control module expect to apply to industrial fields to require the comparatively exact control and monitoring such as multi-motor driving system with inverter, variable air volume system and the boost pump water supply systems.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.69-75
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• 2010

In this paper, a ZigBee-based wireless sensor network is configured for the robot to effectively communicate with the environment platform where sensor nodes are implemented using high performance microcontrollers. The localization and the navigation functions are also required to the robot which performs the given task using various types of sensor information. A new type of ZigBee stack is developed using the RUM(Router Under MAC) of the Atmel Corp. and it is applied to a 32-bit ARM core microcontroller for the high performance sensor data manipulation and transmission. It is verified by experiments that the wireless sensor network consisting of developed high performance sensor nodes can be effectively used for the robot environment platform.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.11
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• pp.521-527
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• 2002

The Hemodialysis system is the device for the patients who have suffered from end stage renal failure as the kidney which removes the waste products in a human body. The existing hemodialysis is based on a 8-bit micro-controller and it is not a touch-screen type but a manual type. This paper is focused on hemodialysis system based on high control and expension embedded system. The whole system consists of main control unit and sub control unit(dialysis control unit, blood control unit, monitoring control unit, networking unit). The dialysis control unit, blood control unit, monitoring control unit are processed by 3 microcontrollers and network unit is for monitoring a renal failure patient's condition. For the evaluation of the system performance, the saline was pured into blood unit and then water removal rate, conductivity and temperature of hemodialysis liquid were measured 10 times in an each state suing the UF pump in the fluid unit varing the quantity of saline to 1000cc, 2000cc, 3000cc and 4000cc. As a result, the rates of water removal are 98.6% in condition of 000cc saline, 96.9% in 2000cc, 98.9% in 3000cc and 98.3% in 4000cc. The conductivities of hemodialysis liquid are 99.6% in the first to third condition and 99.7% in the forth condition. The temperatures of hemodialysis liquid are 99.8% in the first to third condition and 99.6% in th forth condition.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.