• 한국통신학회:학술대회논문집
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• 한국통신학회 1985년도 추계학술발표회 논문집
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• pp.138-143
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• 1985

• 전자공학회논문지B
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• 제28B권7호
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• pp.540-547
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• 1991

This paper proposes a machine in dependent automatic microcode generation system using a microtnstruction description language, MDL. The MDL, which has similar structure to C language, is a high-level microarchitecture description language. It defines the hardwaer elements and the operand selection of microoperartions. The proposed system generates microcode automatically by describing the structure information of a target microarchitectuer and accepting thebehavioral information of microoperations which are generated ad a intermediate language from HLML-C. This proposed system is implemented with C language and YACC on a SUN workstation (4.3 BSD).

• 한국정보통신학회논문지
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• 제26권3호
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• pp.355-366
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• 2022

본 논문은 프로그램 가능한 구조를 사용하여 재구성이 가능하고 저 전력 초소형의 장점을 모두 제공하는 인공지능 가속기를 위한 마이크로코드 기반 뉴럴 네트워크 가속기 컨트롤러를 제안한다. 대상 가속기가 다양한 뉴럴 네트워크 모델을 지원하도록 마이크로코드 컴파일러를 통해 뉴럴 네트워크 모델을 마이크로코드로 변환하여 가속기의 메모리 접근과 모든 연산기를 제어할 수 있다. 200MHz의 System Clock을 기준으로 설계하였으며, YOLOv2-Tiny CNN model을 구동하도록 컨트롤러를 구현하였다. 객체 감지를 위한 VOC 2012 dataset 추론용 컨트롤러를 구현할 경우 137.9ms/image, mask 착용 여부 감지를 위한 mask detection dataset 추론용으로 구현할 경우 99.5ms/image의 detection speed를 달성하였다. 제안된 컨트롤러를 탑재한 가속기를 실리콘칩으로 구현할 때 게이트 카운트는 618,388이며, 이는 CPU core로서 RISC-V (U5-MC2)를 탑재할 경우 대비 약 65.5% 감소한 칩 면적을 제공한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.651-654
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• 1988

This paper proposes a microcode generating system which automatically generates the microcode of various target machine by inputing the intermediate language (MDIL) from the machine independent HLML-C (High Level Microprograming Language C) language. The MOP's (Microoperations) which is modeled 7-tuples generate to extend MDIL by table driven method with the information of translation table for each target machine. As compaction being considered and the hardware resource of target machine used, the conflicts of hardware elements are removed possibly. This proposed system is implemented with C language and yacc on VAX-11/750 (UNIX 4.3 BSD).

• 한국통신학회논문지
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• 제18권10호
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• pp.1527-1536
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• 1993

일반 가전제품, 자동화장치등에 널리 채용된 원격조종기(리모콘)의 응용범위는 더욱 보편화되면서 기능이 다양해지고 있다. 본 논문에서는 다양한 기능에 대응할 수 있는 원격조종기의 새로운 송신회로를 제시하고 있다. 이 회로는 마이크로코드 방식을 채택하여 코드의 변환과 확장, 그리고 펄스폭을 프로그램할 수 있게 하였으며, 프로세싱 회로를 제거하여 소형차가 쉽도록 하였다. 이 회로는 FPGA(Field Programmable Gate Array)를 사용하여 구현하였고 성공적인 동작이 확인되었다.

• 전자공학회논문지B
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• 제31B권10호
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• pp.92-98
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• 1994

In this paper, each step of microprogramming was discussed using a microprogrammable machine that would grasp the characteristics of the microprogram in close relation to the hardwares and microinstruction definable language which make an effective microcode. This was proposed for an environment which minimizes costs.

• 대한의용생체공학회:의공학회지
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• 제6권2호
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• pp.13-14
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• 대한전자공학회논문지
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• 제25권3호
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• pp.276-286
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• 1988

In this paper, HLML-C (High Level Microprogramming Language C) is proposed, which is independent of target machines and has similar strucrure to C language. The HLML-C operations are defined for a abstract machine which contains characteristics of various microarchitectures, and can extend to define a target machine's special operations for efficient microcode generation. A microprogram written in this language is translated into a machine independent intermediate language on abstract machine with the information of a target machine's resource usage and then microoperations of a target machine. The HLML-C compiler is implemented with yacc and C language on VAX-11/750 (4.3 BSD) computer. Through the various test microprogram applied to HLML-C compiler, their results are analyzed.

• 대한의용생체공학회:의공학회지
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• 제6권2호
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• pp.15-22
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.