• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1985.10a
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• pp.138-143
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• 1985

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.7
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• pp.540-547
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• 1991

This paper proposes a machine in dependent automatic microcode generation system using a microtnstruction description language, MDL. The MDL, which has similar structure to C language, is a high-level microarchitecture description language. It defines the hardwaer elements and the operand selection of microoperartions. The proposed system generates microcode automatically by describing the structure information of a target microarchitectuer and accepting thebehavioral information of microoperations which are generated ad a intermediate language from HLML-C. This proposed system is implemented with C language and YACC on a SUN workstation (4.3 BSD).

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.651-654
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• 1988

This paper proposes a microcode generating system which automatically generates the microcode of various target machine by inputing the intermediate language (MDIL) from the machine independent HLML-C (High Level Microprograming Language C) language. The MOP's (Microoperations) which is modeled 7-tuples generate to extend MDIL by table driven method with the information of translation table for each target machine. As compaction being considered and the hardware resource of target machine used, the conflicts of hardware elements are removed possibly. This proposed system is implemented with C language and yacc on VAX-11/750 (UNIX 4.3 BSD).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1527-1536
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• 1993

A new transmitter circuit for remote controllers is designed to provide flexibility and expandibility in function. The circuit employs a microcode approach to accept various code format, length and pulse widths through programming, and the precessing logics is eliminated to reduce its size. The circuit was Implemented using FPGA(Field Programmable Gate Array) and it was found to operate successfully).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.92-98
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• 1994

In this paper, each step of microprogramming was discussed using a microprogrammable machine that would grasp the characteristics of the microprogram in close relation to the hardwares and microinstruction definable language which make an effective microcode. This was proposed for an environment which minimizes costs.

• Journal of Biomedical Engineering Research
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• v.6 no.2
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• pp.13-14
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.3
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• pp.276-286
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• 1988

In this paper, HLML-C (High Level Microprogramming Language C) is proposed, which is independent of target machines and has similar strucrure to C language. The HLML-C operations are defined for a abstract machine which contains characteristics of various microarchitectures, and can extend to define a target machine's special operations for efficient microcode generation. A microprogram written in this language is translated into a machine independent intermediate language on abstract machine with the information of a target machine's resource usage and then microoperations of a target machine. The HLML-C compiler is implemented with yacc and C language on VAX-11/750 (4.3 BSD) computer. Through the various test microprogram applied to HLML-C compiler, their results are analyzed.

• Journal of Biomedical Engineering Research
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• v.6 no.2
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• pp.15-22
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• 1985

We have developed a microprogramir!able signal processor for real-time ultrasonic signal processing. Processing speed was increased by the parallelism in horizontal microprogram using 104bits microcode and the Pipelined architecture. Control unit of the signal processor was designed by microprogrammed architec- ture and writable control store (WCS) which was interfaced with host computer, APPLE- ll . This enables the processor to develop and simulate various digital signal processing algorithms. The performance of the processor was evaluated by the Fast Fourier Transform (FFT) program. The execution time to perform 16 bit 1024 points complex FF7, radix-2 DIT algorithm, was about 175 msec with IMHz master Clock. We can use this processor to Bevelop more efficient signal processing algorithms on the biological signal processing.