• 한국생산제조학회지
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• 제23권6호
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• pp.636-641
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• 2014

This paper discusses the fabrication process for a Nipkow disk using micro-lens and pinhole disks. The confocal measuring system that uses the Nipkow disk has the advantage in measuring speed, because the Nipkow disk can simultaneously provide confocal images of all pixels in a CCD camera without requiring a lateral scanning unit. A micro-lens configuration, which focuses illumination on a pinhole, overcomes the low optical efficiency of the Nipkow disk system and allows its use in practical applications. This paper describes how to design the Nipkow disk in terms of numerical aperture, particularly for measuring the height of solder bumps in packaging application and for hybrid processes combining mechanical and semiconductor processes.

• 정보저장시스템학회논문집
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• 제3권3호
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• pp.139-143
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• 2007

In recent years new recording media and materials for head-disk interface (HDI) have been developed in order to increase the recording density of storage devices and decrease the cost of production. It is well known that HDI in hard disk drive (HDD) needs high durability and stability. The tribological characteristic of commercialized HDI systems is an important indicator of the HDD reliability. In this study, experimental investigation on the wear coefficient of commercialized hard disk slider pads was performed. The slider was placed on top of a hard disk and allowed to slide for a set distance. The wear of the pads was measured after the sliding tests. The result showed that the micro-bumps in commercialized HDD have extremely low wear coefficient of $10^{-11}$. The results of this work may be used for further development of the HDI technology for HDD.

• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.53-57
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• 2011

In the modern packaging technologies highly condensed metal interconnects are typically formed by highcost processes. These methods inevitably require the precise controls of mutually dependant process parameters, which usually cause the difficulty of the change in the layout design for interconnects of chip to-chip, or chip-to-substrate. In order to overcome these problems, the unique concept and methodology of self-assembly even in micro-meter scale were developed. In this report we focus on the factors which influenced the self-formed bumps by analyzing the phenomenon experimentally. In case of RMA flux, homogenous pattern was obtained in both plain surface and cross-section surface observation. By using RA flux, the phenomena were accelerated although the self-formtion results was inhomogenous. With ussage of moderate RA flux, reaction rate of the self-formation was accelerated with homogeneous pattern.

• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Current Applied Physics
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• 제18권11호
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• pp.1261-1267
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• 2018

In this paper, an off-axis digital holographic microscopy compensated with self-hologram rotation is presented. The process is implemented via subtracting the unwrapped phase maps of the off-axis parabolic hologram and its rotation $180^{\circ}$ to eliminate the tilt induced by the angle between the spherical object wave O and the plane reference wave R. Merit of the proposed method is that it can be done without prior knowledge of physical parameters and hence can reconstruct a parabolic hologram of $1024{\times}768$ pixels within tens of milliseconds since it doesn't require a digital reference wave. The method is applied to characterize rough gold bumps and the obtained results were compared with those extracted from the conventional reconstruction method. The comparison showed that the proposed method can characterize rough surfaces with excellent contrast and in realtime. Merit of the proposed method is that it can be used for monitoring smaller biological cells and micro-fluidic devices.

• Elastomers and Composites
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• 제58권1호
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• pp.17-25
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• 2023

Abrasion tests of model tire tread compounds (NR and NR/BR blend compounds) were performed at different slip angles (1° and 7°) using a laboratory abrasion tester. The abrasion behavior was investigated by analyzing the worn surface and wear particles. The abrasion spacing formed on the specimen worn at the large slip angle of 7° was significantly narrower than that at the small slip angle of 1°, while the abrasion depth for the specimen worn at 7° was lower than that at 1°. The abrasion spacing and depth tended to be narrower and lower, respectively, as the BR content increased. The abrasion patterns were clearly visible on the outside of the specimen for the slip angle of 1° but not for 7°. The wear particles had a rough surface and there were numerous micro-bumps. It was found that the crosslink density affected the abrasion patterns and morphologies of the wear particles.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• 마이크로전자및패키징학회지
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• 제14권4호
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• pp.79-85
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• 2007

본 연구의 목적은 OSP, 전해 Au과 무전해 Ni/Au로써 표면처리를 달리한 연성회로기판 상에 Au 스터드 플립칩 범프의 초음파 접합 가능성을 연구하는 것이었다. Au 스터드 범프는 표면처리 방법에 상관없이 성공적으로 연성회로기판의 패드 상에 초음파 접합되었다 접합 강도는 접합 시간에 민감하게 영향을 받았다. 접합 시간이 길어짐에 따라 접합 강도는 증가하였으나, 2초 이상의 접합 시간에서는 이웃 범프끼리 단락되는 bridge 현상이 발생하였다. 최적 접합조건은 OSP 처리된 가판상에 0.5초간 초음파 접합하는 것이었다.

• Design & Manufacturing
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• 제13권4호
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• pp.10-16
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• 2019

Semiconductor chip is bonded to the substrate by melting solder bumps. In general, the chip bonding is applied by a Reflow process or a Thermo-Compression(TC) bonding process. In this paper, we introduce a Laser Assisted Thermo-Compression bonding (LATCB) process to improve the anxiety of the existing process(Reflow, TC bonding). In the LATCB process, the chip is bonded to the substrate by irradiating a laser with a uniform energy density in the same area as the chip to melt only the solder bumps and press the chip with a Transparent Compression Module (TCM). The TCM consists of a fused silica header for penetrating the laser and pressurizing the chip, and a piezoelectric actuator (P.A.) coupled to both ends of the header for micro displacement control of the header. In addition, TCM is a structure that can pressurize the chip and deliver it to the chip and solder bumps without losing the energy of the laser. Fused silica, which is brittle, is vulnerable to deformation, so the header may be damaged when an external force is applied for pressurization or a displacement differenced is caused by piezoelectric actuators at both ends. On the other hand, in order to avoid interference between the header and the adjacent chip when pressing the chip using the TCM, the header has a notch at the bottom, and breakage due to stress concentration of the notch is expected. In this study, the thickness and notch length that the header does not break when the external force (500 N) is applied to both ends of the header are optimized using structural analysis and Coulomb-Mohr failure theory. In addition, the maximum displacement difference of the P.A.s at both ends where no break occurred in the header was derived. As a result, the thickness of the header is 11 mm, and the maximum displacement difference between both ends is 8 um.

• 마이크로전자및패키징학회지
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• 제19권2호
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• pp.67-72
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• 2012

최근에 전자 산업 분야에서 장치의 고용량을 구현 하기 위해 구동 drive IC의 선폭은 좁아지고 집적도는 증가하고 있다. 이러한 반도체, 전자 산업 분야의 초소형화, 고밀도화에 따라 FCCL(Flexible Copper Clad Laminate)의 표면 품질이 더욱 중요해 지고 있다. FCCL의 표면 결함으로는 돌기, 스크레치, 덴트 등이 있다. 특히 돌기가 표면에 존재할 경우 후속 공정에서 쇼트와 같은 불량을 유발할 수 있으며, 제품의 품질 저하를 야기 시킬 수 있다. 하지만 표면에 돌기가 존재한다 하더라도, 전해액의 레벨링 특성이 우수하다면 돌기의 성장을 막을 수 있다.평탄하고, 결함이 없는 도금표면을 얻기 위해서는 첨가제의 역할이 필수적이다. 평탄한 구리 표면을 형성하기 위해서 stock solution에 가속제, 억제제, 레벨러를 첨가하였다. 레벨러를 첨가하는 이유는 평탄한 표면을 얻고, 돌기의 형성을 억제하기 위함이다. 구리도금 표면 형상을 향상시키기 위한 레벨러로는 SO(Safranin O), MV(Methylene Violet), AB(Alcian Blue), JGB(Janus Green B), DB(Diazine Black) and PVP(Polyvinyl Pyrrolidone)가 사용되었다. 도금 첨가제와 도금 조건의 변화를 통해 도금시레벨링 특성을 향상시키고, 레벨링 특성 측정을 위해 니켈 인공돌기를 제작 한 후 레벨링 특성을 측정하였다.