• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.23 no.6
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• pp.636-641
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• 2014

This paper discusses the fabrication process for a Nipkow disk using micro-lens and pinhole disks. The confocal measuring system that uses the Nipkow disk has the advantage in measuring speed, because the Nipkow disk can simultaneously provide confocal images of all pixels in a CCD camera without requiring a lateral scanning unit. A micro-lens configuration, which focuses illumination on a pinhole, overcomes the low optical efficiency of the Nipkow disk system and allows its use in practical applications. This paper describes how to design the Nipkow disk in terms of numerical aperture, particularly for measuring the height of solder bumps in packaging application and for hybrid processes combining mechanical and semiconductor processes.

• Transactions of the Society of Information Storage Systems
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• v.3 no.3
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• pp.139-143
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• 2007

In recent years new recording media and materials for head-disk interface (HDI) have been developed in order to increase the recording density of storage devices and decrease the cost of production. It is well known that HDI in hard disk drive (HDD) needs high durability and stability. The tribological characteristic of commercialized HDI systems is an important indicator of the HDD reliability. In this study, experimental investigation on the wear coefficient of commercialized hard disk slider pads was performed. The slider was placed on top of a hard disk and allowed to slide for a set distance. The wear of the pads was measured after the sliding tests. The result showed that the micro-bumps in commercialized HDD have extremely low wear coefficient of $10^{-11}$. The results of this work may be used for further development of the HDI technology for HDD.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.53-57
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• 2011

In the modern packaging technologies highly condensed metal interconnects are typically formed by highcost processes. These methods inevitably require the precise controls of mutually dependant process parameters, which usually cause the difficulty of the change in the layout design for interconnects of chip to-chip, or chip-to-substrate. In order to overcome these problems, the unique concept and methodology of self-assembly even in micro-meter scale were developed. In this report we focus on the factors which influenced the self-formed bumps by analyzing the phenomenon experimentally. In case of RMA flux, homogenous pattern was obtained in both plain surface and cross-section surface observation. By using RA flux, the phenomena were accelerated although the self-formtion results was inhomogenous. With ussage of moderate RA flux, reaction rate of the self-formation was accelerated with homogeneous pattern.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Current Applied Physics
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• v.18 no.11
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• pp.1261-1267
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• 2018

In this paper, an off-axis digital holographic microscopy compensated with self-hologram rotation is presented. The process is implemented via subtracting the unwrapped phase maps of the off-axis parabolic hologram and its rotation $180^{\circ}$ to eliminate the tilt induced by the angle between the spherical object wave O and the plane reference wave R. Merit of the proposed method is that it can be done without prior knowledge of physical parameters and hence can reconstruct a parabolic hologram of $1024{\times}768$ pixels within tens of milliseconds since it doesn't require a digital reference wave. The method is applied to characterize rough gold bumps and the obtained results were compared with those extracted from the conventional reconstruction method. The comparison showed that the proposed method can characterize rough surfaces with excellent contrast and in realtime. Merit of the proposed method is that it can be used for monitoring smaller biological cells and micro-fluidic devices.

• Elastomers and Composites
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• v.58 no.1
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• pp.17-25
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• 2023

Abrasion tests of model tire tread compounds (NR and NR/BR blend compounds) were performed at different slip angles (1° and 7°) using a laboratory abrasion tester. The abrasion behavior was investigated by analyzing the worn surface and wear particles. The abrasion spacing formed on the specimen worn at the large slip angle of 7° was significantly narrower than that at the small slip angle of 1°, while the abrasion depth for the specimen worn at 7° was lower than that at 1°. The abrasion spacing and depth tended to be narrower and lower, respectively, as the BR content increased. The abrasion patterns were clearly visible on the outside of the specimen for the slip angle of 1° but not for 7°. The wear particles had a rough surface and there were numerous micro-bumps. It was found that the crosslink density affected the abrasion patterns and morphologies of the wear particles.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.79-85
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• 2007

This study was focused on the feasibility of ultrasonic bonding of Au stud flip chip bumps on the flexible printed circuit board (FPCB) with three different surface finishes: organic solderability preservative (OSP), electroplated Au and electroless Ni/immersion Au (ENIG). The Au stud flip chip bumps were successfully bonded to the bonding pads of the FPCBs, irrespective of surface finish. The bonding time strongly affected the joint integrity. The shear force increased with increasing bonding time, but the 'bridge' problem between bumps occurred at a bonding time over 2 s. The optimum condition was the ultrasonic bonding on the OSP-finished FPCB for 0.5 s.

• Design & Manufacturing
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• v.13 no.4
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• pp.10-16
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• 2019

Semiconductor chip is bonded to the substrate by melting solder bumps. In general, the chip bonding is applied by a Reflow process or a Thermo-Compression(TC) bonding process. In this paper, we introduce a Laser Assisted Thermo-Compression bonding (LATCB) process to improve the anxiety of the existing process(Reflow, TC bonding). In the LATCB process, the chip is bonded to the substrate by irradiating a laser with a uniform energy density in the same area as the chip to melt only the solder bumps and press the chip with a Transparent Compression Module (TCM). The TCM consists of a fused silica header for penetrating the laser and pressurizing the chip, and a piezoelectric actuator (P.A.) coupled to both ends of the header for micro displacement control of the header. In addition, TCM is a structure that can pressurize the chip and deliver it to the chip and solder bumps without losing the energy of the laser. Fused silica, which is brittle, is vulnerable to deformation, so the header may be damaged when an external force is applied for pressurization or a displacement differenced is caused by piezoelectric actuators at both ends. On the other hand, in order to avoid interference between the header and the adjacent chip when pressing the chip using the TCM, the header has a notch at the bottom, and breakage due to stress concentration of the notch is expected. In this study, the thickness and notch length that the header does not break when the external force (500 N) is applied to both ends of the header are optimized using structural analysis and Coulomb-Mohr failure theory. In addition, the maximum displacement difference of the P.A.s at both ends where no break occurred in the header was derived. As a result, the thickness of the header is 11 mm, and the maximum displacement difference between both ends is 8 um.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.67-72
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• 2012

In recent days, the wire width of IC is narrowed and the degree of integration of IC is increased to obtain the higher capacity of the devices in electronic industry. And then the surface quality of FCCL(Flexible Copper Clad Laminate) became increasingly important. Surface defects on FCCL are bump, scratch, dent and so on. In particular, bumps cause low reliability of the products. Even though there are bumps on the surface, if leveling characteristic of plating solution is good, it does not develop significant bump. In this study, the leveling characteristics of additives are investigated. The objective of study is to improve the leveling characteristic and reduce the surface step through additives and plating conditions. The additives in the electrodeposition bath are critical to obtain flat surface and free of defects. In order to form flat copper surface, accelerator, suppressor and leveler are added to the stock solution. The reason for the addition of leveler is planarization surface and inhibition of the formation of micro-bump. Levelers (SO(Safranin O), MV(Methylene Violet), AB(Alcian Blue), JGB(Janus Green B), DB(Diazine Black) and PVP(Polyvinyl Pyrrolidone) are used in copper plating solution to enhance the morphology of electroplated copper. In this study, the nucleation and growth behavior of copper with variation of additives are studied. The leveling characteristics are analyzed on artificially fabricated Ni bumps.