• Journal of the Korean Society of Manufacturing Process Engineers
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• v.15 no.1
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• pp.8-13
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• 2016

The micro drill bit automatic regrinding in-line system is a system that refurbishes drill bits used in a PCB manufacturing process. This system is able to refurbish drill bits with a minimum size of ø0.15-0.075mm that have previously been discarded. Beyond the conventional manual cleaning process using ultrasound, this system adopts a water jet cleaning system, making it capable of cleaning drill bits with a minimum size of ø0.15-0.075mm. This paper analyses various contact pressures applied to the surface of drill bits depending on the shooting pressure of the cleaning device and fluid velocity in order to optimize the nozzle location and to detect structural instability caused by the contact pressures.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.163-167
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• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.142-151
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• 1995

The trend of compact size, light weight, low power consumption in the portable telecommunication equipments demands large scale integration and low voltage operation of chips and the minimization of the number of the components in the telecommunication terminal. According to the trend, existing chip components are modulized and are integrated as a part into a bigger chip. This paper is about the development of the peripheral units of micro-controller for mobile telecommunication terminal. Peripherals consist of DMA controller, Interrupt controller, timer, watchdog timer, clock generator, and power management unit. They are designed to be integrated with EU(Execution Unit) and BIU(Bus Interface Unit) into a 16 bit micro-controller which will be used as a core of an ASIC for next generation digital mobile telecommunication terminal. At first, whole block of the micro-controller was described by VHDL behavioral model and simulated to verify its overall operation. Then, watchdog timer, clock generator and power management unit were directly synthesized by using VHDL synthesis tool. Rest of the pheriperal units were designed and simulated by using Compass Design Tool.

• Convergence Security Journal
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• v.14 no.5
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• pp.17-24
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• 2014

This study proposed LDP (Local Directional Pattern) as a new local micro pattern for facial expression recognition to solve noise sensitive problem of LBP (Local Binary Pattern). The proposed method extracts 8-directional components using $m{\times}m$ mask to solve LBP's problem and choose biggest k components, each chosen component marked with 1 as a bit, otherwise 0. Finally, generates a pattern code with bit sequence as 8-directional components. The result shows better performance of rotation and noise adaptation. Also, a new local facial feature can be developed to present both PFF (permanent Facial Feature) and TFF (Transient Facial Feature) based on the proposed method.

• Journal of Korean Electronics
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• v.7 no.11
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• pp.99-99
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• 1987

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.346-349
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• 2011

In this paper, we design a perceptually invisible dot pattern layout and its recognition scheme, and we apply the recognition scheme into a smart self learning aid for interactive learning aid. To increase maximum information capacity and also increase robustness to the noises, we design a ECC (error correcting code) based dot pattern with directional vector indicator. To make a smart self-learning aid, we embed the micro dot pattern (20 information bit + 15 ECC bits + 9 layout information bit) using K ink (CMYK) and extract the dot pattern using IR (infrared) LED and IR filter based camera, which is embedded in the smart pen. The reason we use K ink is that K ink is a carbon based ink in nature, and carbon is easily recognized with IR even without light. After acquiring IR camera images for the dot patterns, we perform layout adjustment using the 9 layout information bit, and extract 20 information bits from 35 data bits which is composed of 20 information bits and 15 ECC bits. To embed and extract information bits, we use topology based dot pattern recognition scheme which is robust to geometric distortion which is very usual in camera based recognition scheme. Topology based pattern recognition traces next information bit symbols using topological distance measurement from the pivot information bit. We implemented and experimented with sample patterns, and it shows that we can achieve almost 99% recognition for our embedding patterns.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.165-167
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• 2006

In this paper we present a new-generation sensor network processor which is not optimized in circuit level, but in system architecture level. The new design build on a conventional processor architecture, improving the design by focusing on application oriented specification, ISA, and micro-architectural optimization that reduce overall design size and advance energy-per-instruction. The design employs harvard architecture, 8-bit data paths, and an compact 19 bit wide RISC ISA. The design also features a unique interrupt handler which offloads periodical monitoring jobs from the main part of CPU. Our most efficient design is capable of running at 300 KHz (0.3 MIPS) while consuming only about few pJ/instruction.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.