• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.130-137
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• 1995

Deopsition of thermal quality SiO2 using a high density plasma ECR CVD process has been demonstrated to give void and seam free gap fill of high aspect ratio metallization structures with a simple oxygen-silane chemistry. This is achieved by continuous sputter etching of the film during the deposition process. A two-step process is utilized to deposit a composite layer for higher manufacturing efficiency. The first step, which has a deposition rate of approximately 0.5 $\mu$m/min., is used to provide complete gap fill between the metal lines. The second step, which has a deposition rate of up to 1.5 $\mu$m/min., is used to deposit a total thickness of 2.0$\mu$m for the intermetal dielectric film. The topography of this composite film is very compatible with subsequent chemicl mechanical polishing(CMP) planarization processing.

• Journal of the Korean institute of surface engineering
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• v.36 no.5
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• pp.373-378
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• 2003

With increasing environmental concerns, application of lead-free solder and fluxless soldering process have been taken attention from the electronic packaging industry. Plasma treatment is one of the soldering methods for the fluxless soldering, and it can prevent environmental pollution cased by flux. On this study fluxless soldering process under $Ar-H_2$plasma using lead free solders such as Sn-3.5 wt%Ag, Sn-3.5 wt%Ag-0.7 wt%Cu and Sn-37%Pb for a reference was investigated. As the plasma reflow has higher soldering temperature than normal air reflow, the effects of UBM(Under Bump Metallization) thickness on the interfacial reaction and bonding strength can be critical. Experimental results showed in case of the thin UBM, Au(20 nm)/Cu(0.3 $\mu\textrm{m}$)/Ni(0.4 $\mu\textrm{m}$)/Al(0.4 $\mu\textrm{m}$), shear strength of the soldered joint was relatively low as 19-27㎫, and it's caused by the crack observed along the bonded interface. The crack was believed to be produced by the exhaustion of the thin UBM-layer due to the excessive reaction with solder under plasma. However, in case of thick UBM, Au(20 nm)/Cu(4 $\mu\textrm{m}$)/Ni(4 $\mu\textrm{m}$)/Al(0.4 $\mu\textrm{m}$), the bonded interface was sound without any crack and shear strength gives 32∼42㎫. Thus, by increasing UBM thickness in this study the shear strength can be improved to 50∼70%. Fluxed reflow soldering under hot air was also carried out for a reference, and the shear strength was 48∼52㎫. Consequently the fluxless soldering with plasma showed around 65∼80% as those of fluxed air reflow, and the possibility of the $Ar-H_2$ plasma reflow was evaluated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.3-4
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• 2006

In this paper, a nickel silicide technology with post-silicidation annealing effect for thin film SOI devices is investigated in detail. Although lower resistivity Ni silicide can be easily obtained at low forming temperature, poor thermal stability and changing of characteristic are serious problems during the post silicidation annealing like ILD (Inter Layer Dielectric) deposition or metallization. So these effects are observed as deposited Ni thickness differently on As doped SOI (Si film 30nm). Especially, the sheet resistance of Ni thickness deposited 20nm was lower than 30nm before the post silicidation annealing. But after the post silicidation annealing, the sheet resistance was changed. Therefore, in thin film SOI MOSFETs or Ni-FUSI technology that the Si film is less than 50nm, it is important to decide the thickness of deposited Ni in order to avoid forming high resistivity silicide.

• Current Photovoltaic Research
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• v.4 no.1
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• pp.12-15
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• 2016

Screen printing technique followed by firing has commonly been used as metallization for both laboratory and industrial based solar cells. In the solar cell industry, the firing process is usually conducted in a belt furnace and needs to be optimized for fabricating high efficiency solar cells. The printed-Al layer on the silicon is rapidly heated at over $800^{\circ}C$ which forms a layer of back surface field (BSF) between Si-Al interfaces. The BSF layer forms $p-p^+$ structure on the rear side of cells and lower rear surface recombination velocity (SRV). To have low SRV, deep $p^+$ layer and uniform junction formation are required. In this experiment, firing process was carried out by using conventional tube furnace with $N_2$ gas atmosphere to optimize $V_{oc}$ of laboratory cells. To measure the thickness of BSF layer, selective etching was conducted by using a solution composed of hydrogen fluoride, nitric acid and acetic acid. The $V_{oc}$ and pseudo efficiency were measured by Suns-$V_{oc}$ to compare cell properties with varied firing condition.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.243.2-243.2
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• 2016

Tungsten (W) is recently gaining attention as a potential candidate to replace Cu in semiconductor metallization due to its expected improvement in material reliability and reduced resistivity size effect. In this study, the impact of electron scattering at grain boundaries in a polycrystalline W thin film was investigated. Two nominally 300 nm-thick films, a (110)-oriented single crystal film and a (110)-textured polycrystalline W film, were prepared onto (11-20) Al2O3 substrate and thermally oxidized Si substrate, respectively in identical fabrication conditions. The lateral grain size for the polycrystalline film was determined to be $119{\pm}7nm$ by TEM-based orientation mapping technique. The film thickness was chosen to significantly exceed the electron mean free path in W (16.1 and 77.7 nm at 293 and 4.2 K, respectively), which allows the impact of surface scattering on film resistivity to be negligible. Then, the difference in the resistivity of the two films can be attributed to grain boundary scattering. quantitative analyses were performed by employing the Mayadas-Shatzkes (MS) model, where the grain boundary reflection coefficient was determined to be $0.42{\pm}0.02$ and $0.40{\pm}0.02$ at 293 K and 4.2 K, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.29-29
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• 1999

The synthesis of layered structures on the nanometer scale has become essential for continued improvements in the operation of various electronic and magnetic devices. Abrupt metal-metal interfaces are desired for applications ranging from metallization in semiconductor devices to fabrication of magnetoresistive tunnel junctions for read heads on magnetic disk drives. In particular, characterizing the interface structure between various transition metals (TM) and aluminum is desirable. We have used the techniques of MeV ion backscattering and channeling (HEIS), x-ray photoemission (ZPS), x-ray photoelectron diffraction(XPD), low-energy ion scattering (LEIS), and low-energy electron diffraction(LEED), together with computer simulations using embedded atom potentials, to study solid-solid interface structure for thin films of Ni, Fe, Co, Pd, Ti, and Ag on Al(001), Al(110) and Al(111) surfaces. Considerations of lattice matching, surface energies, or compound formation energies alone do not adequately predict our result, We find that those metals with metallic radii smaller than Al(e.g. Ni, Fe, Co, Pd) tend to form alloys at the TM-Al interface, while those atoms with larger atomic radii(e.g. Ti, Ag) form epitaxial overlayers. Thus we are led to consider models in which the strain energy associated with alloy formation becomes a kinetic barrier to alloying. Furthermore, we observe the formation of metastable fcc Ti up to a critical thickness of 5 monolayers on Al(001) and Al(110). For Ag films we observe arbitrarily thick epitaxial growth exceeding 30 monolayers with some Al alloying at the interface, possible driven by interface strain relief. Typical examples of these interface structures will be discussed.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.292-292
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• 2014

Wide band gap semiconductors, such as III-nitrides (GaN, AlN, InN, and their alloys), SiC, and diamond are expected to play an important role in the next-generation electronic devices. Specifically, GaN-based high electron mobility transistors (HEMTs) have been targeted for high power, high frequency, and high temperature operation electronic devices for mobile communication systems, radars, and power electronics because of their high critical breakdown fields, high saturation velocities, and high thermal conductivities. For the stable operation, high power, high frequency and high breakdown voltage and high current density, the fabrication methods have to be optimized with considerable attention. In this study, low ohmic contact resistance and smooth surface morphology to AlGaN/GaN on 2 inch c-plane sapphire substrate has been obtained with stepwise annealing at three different temperatures. The metallization was performed under deposition of a composite metal layer of Ti/Al/Ni/Au with thickness. After multi-layer metal stacking, rapid thermal annealing (RTA) process was applied with stepwise annealing temperature program profile. As results, we obtained a minimum specific contact resistance of $1.6{\times}10^{-7}{\Omega}cm2$.

• Korea-Australia Rheology Journal
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• v.14 no.2
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• pp.63-70
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• 2002

Chemical mechanical planarization (CMP) is the polishing process enabled by both chemical and mechanical actions. CMP is used in the fabrication process of the integrated circuits to achieve adequate planarity necessary for stringent photolithography depth of focus requirements. And recently copper is preferred in the metallization process because of its low resistivity. We have studied the effects of chemical reaction on the polishing rate and surface planarity in copper CMP by means of numerical simulation solving Navier-Stokes equation and copper diffusion equation. We have performed pore-scale simulation and integrated the results over all the pores underneath the wafer surface to calculate the macroscopic material removal rate. The mechanical abrasion effect was not included in our study and we concentrated our focus on the transport phenomena occurring in a single pore. We have observed the effects of several parameters such as concentration of chemical additives, relative velocity of the wafer, slurry film thickness or ash)tract ratio of the pore on the copper removal rate and the surface planarity. We observed that when the chemical reaction was rate-limiting step, the results of simulation matched well with the experimental data.

• Journal of the Korean institute of surface engineering
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• v.36 no.5
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• pp.386-392
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• 2003

The electroplating process for a solder bump which can be applied for a flip chip was studied. Si-wafer was used for an experimental substrate, and the substrate were coated with UBM (Under Bump Metallization) of Al(400 nm)/Cu(300 nm)Ni(400 nm)/Au(20 nm) subsequently. The compositions of the bump were Sn-Cu and eutectic Sn-Pb, and characteristics of two bumps were compared. Experimental results showed that the electroplated thickness of the solders were increased with time, and the increasing rates were TEX>$0.45 <\mu\textrm{m}$/min for the Sn-Cu and $ 0.35\mu\textrm{m}$/min for the Sn-Pb. In the case of Sn-Cu, electroplating rate increased from 0.25 to $2.7\mu\textrm{m}$/min with increasing current density from 1 to 8.5 $A/dm^2$. In the case of Sn-Pb the rate increased until the current density became $4 A/dm^2$, and after that current density the rate maintains constant value of $0.62\mu\textrm{m}$/min. The electro plated bumps were air reflowed to form spherical bumps, and their bonded shear strengths were evaluated. The shear strength reached at the reflow time of 10 sec, and the strength was of 113 gf for Sn-Cu and 120 gf for Sn-Pb.

• 한국태양에너지학회:학술대회논문집
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• 2011.04a
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• pp.116-120
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• 2011

In this paper, we studied the optimization of the screen pringting method for crystalline silicon solar cell fabrication. The 156 * 156 mm2 p-type silicon wafers with $200{\mu}m$ thickness and $0.5-3{\Omega}cm$ resistivity were used after texturing, doping, and passivation. Screen printing method is a common way to make the c-Si solar cell with low-cost and high-efficiency. We studied the optimized condition for screen printing with crystalline silicon solar cell as changing the printing direction (finger line or bus bar), finger width, and mesh angle. As a result, the screen printing with finger line direction showed higher finger height and better conversion efficiency, compared with one with bus bar direction. The experiments with various finger widths and mesh angles were also carried out. The characteristics of solar cells was obtained by measuring light current-voltage, optical microscope and electroluminescence.