• Transactions on Electrical and Electronic Materials
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• 제12권6호
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• pp.262-266
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• 2011

A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.

• 센서학회지
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• 제15권2호
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• pp.102-105
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• 2006

In-vivo dosimetry is an essential tool of quality assurance programs in radiotherapy. The most commonly used techniques to verify dose are thermoluminescence dosimeter (TLD) and diode detectors. Metal oxide semiconductor field-effect transistor (MOSFET) has been recently proposed for using in radiation therapy with many advantages. The reproducibility, linearity, isotropy, dose rate dependence of the MOSFET dosimeter were studied and its availability was verified. Consequently the results can be used to improve therapeutic planning procedure and minimize treatment errors in radiotherapy.

• 전자통신동향분석
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• 제4권3호
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• pp.106-120
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• 1989

반도체 집적회로(IC)가 고집적화됨에 따라 소자는 계속 축소화되고 이에 따른 소자 제조공정은 더욱 엄격하고 복잡해지고 있다. 그 중 절연막 분야에서는 MOSFET(metal-oxide-semiconductor field-effect transistor) 소자의 절연막과 기억소자에서의 capacitor 절연막의 초박막화와 고신뢰화가 매우 주목 받고 있는 분야이다. 본 고에서는 지난 1989년 5월 Kyoto에서 IEEE Electron Device Society와 일본 응용물리학회가 공동주최로 개최된 '1989 Symposium on VLSI Technology' 에서 발표된 논문 중에서 절연막에 관련된 논문을 분석 정리함으로써 절연막에 대한 최근 기술 동향을 파악하고자 하였다.

• ETRI Journal
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• 제11권3호
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• pp.11-22
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• 1989

Stress에 잘 견딜 수 있는 metal-oxide-semiconductor field effect transistor(MOSFET)의 매우 얇고(10mm 이하) 고신뢰성을 갖는 게이트 절연막을 개발하기 위해서 급속열처리법을 이용하여 제조한 재산화질화산화막의 특성에 관하여 연구하였다. AES 분석에 의하여 8nm 두께의 초기산화막을 질화시킬 때 산화막의 계면이 우선적으로 질화가 일어났으며, 질화된 막을 재산화시킬 때 표면과 계면의 [N]가 감소하였다. 또한 재산화시킬 경우 두께가 약간 증가함을 보였으며, 질화가 강하게 될수록 두께 증가는 크지 않았다. 전기적 특성으로써 I-V 특성과 고주파(1MHz) C-V 특성, 정전류 stress 후의 고주파 C-V 특성 변화 들을 조사한 결과 $950^{\circ}C$ 60초 동안 질화시킨 재산화질화산화막($ONO_L막$) 은 정전류 stress에 대하여 flat band 전압 변화에 계면 상태 밀도(interface state density)변화가 적고, 절연파괴전압(breakdown voltage)특성 등이 우수하게 나타났다.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2002년도 추계학술대회논문집
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• pp.204-209
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• 2002

A PDP(Plasma Display Panel) module consists of a discharge panel, a SMPS(Switched Mode Power Supply) for power supply, driving boards for panel control, and a logic board. Driving boards supply high voltage pulses to induce glow discharge in the PDP panel. The electrical pulses excite the circuit elements and subsequently generate acoustic noises. The main sources of the noise in the circuit are the transformer of SMPS and the power MOSFET(Metal Oxide Semiconductor Field Effect Transistor) of driving boards, and the heat sinks often amplify the noise level. The reduction of the acoustic noises was achieved by modifying both the structural and circuit elements. The structural method was executed by the improvement of heat sinks. The optimization of SMPS and condensers was carried out for the circuit elements.

• 전기전자학회논문지
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• 제22권3호
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• pp.565-569
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• 2018

For the conventional power MOSFET (metal-oxide semiconductor field-effect transistor) device structure, there exists a tradeoff relationship between specific on-state resistance (Ron,sp) and breakdown voltage (BV). In order to overcome this tradeoff, a super-junction (SJ) trench MOSFET (TMOSFET) structure with uniform or non-uniform doping concentration, which decreases linearly in the vertical direction from the N drift region at the bottom to the channel at the top, for an optimal design is suggested in this paper. The on-state resistance of $0.96m{\Omega}-cm2$ at the SJ TMOSFET is much less than that at the conventional power MOSFET under the same breakdown voltage of 100V. A design methodology for the edge termination is proposed to achieve the same breakdown voltage and on-state resistance as the main body of the super-junction TMOSFET by using of the SILVACO TCAD 2D device simulator, Atlas.

• 한국전기전자재료학회논문지
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• 제25권4호
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• pp.270-275
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• 2012

Power MOSFET(metal oxide silicon field effect transistor) operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. But on-resistance characteristics depending on the increasing breakdown voltage spikes is a problem. So 600 V planar power MOSFET compare to 1/3 low on-resistance characteristics of super junction MOSFET structure. In this paper design to 600 V planar MOSFET and super junction MOSFET, then improvement of comparative analysis breakdown voltage and resistance characteristics. As a result, super junction MOSFET improve on about 40% on-state voltage drop performance than planar MOSFET.

• 정보저장시스템학회:학술대회논문집
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• 정보저장시스템학회 2005년도 추계학술대회 논문집
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• pp.56-58
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• 2005

To illustrate an application of the field effect transistor (FET) structure, this study suggests a new cantilever, using atomic force microscopy (AFM), for sensing surface potentials in nanoscale. A combination of the micro-electromechanical system technique for surface and bulk and the complementary metal oxide semiconductor process has been employed to fabricate the cantilever with a silicon-on-insulator (SOI) wafer. After the implantation of a high-ion dose, thermal annealing was used to control the channel length between the source and the drain. The basic principle of this cantilever is similar to the FET without a gate electrode.

• 전력전자학회논문지
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• 제25권5호
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• pp.350-357
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• 2020

This study presents the design of an 18 kW two-phase interleaved buck converter that uses a coupled inductor for an electric vehicle rapid charger. The designs of a two-phase coupled inductor for current ripple and physical size reduction and a two-phase interleaved buck converter based on silicon carbide metal - oxide - semiconductor field-effect transistor for high efficiency were described in detail. The operating principle of the two-phase interleaved buck converter was analyzed, and the coupled inductor was investigated using a magnetized equivalent circuit. Simulation and experiments were conducted to verify the validity of the proposed two-phase interleaved buck converter, and the theoretical design method and experimental results were confirmed.

• ETRI Journal
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• 제32권4호
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• pp.530-539
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• 2010

As the conventional silicon metal-oxide-semiconductor field-effect transistor (MOSFET) approaches its scaling limits, quantum mechanical effects are expected to become more and more important. Accurate quantum transport simulators are required to explore the essential device physics as a design aid. However, because of the complexity of the analysis, it has been necessary to simulate the quantum mechanical model with high speed and accuracy. In this paper, the modeling of double gate MOSFET based on an adaptive neuro-fuzzy inference system (ANFIS) is presented. The ANFIS model reduces the computational time while keeping the accuracy of physics-based models, like non-equilibrium Green's function formalism. Finally, we import the ANFIS model into the circuit simulator software as a subcircuit. The results show that the compact model based on ANFIS is an efficient tool for the simulation of nanoscale circuits.