• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.93-101
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• 2002

We have proposed and fabricated two lateral type field emission diodes, poly-Si emitter by utilizing the local oxidation of silicon (LOCOS) and GaN emitter using metal organic chemical vapor deposition (MOCVD) process. The fabricated poly-Si diode exhibited excellent electrical characteristics such as a very low turn-on voltage of 2 V and a high emission current of $300{\;}\bu\textrm{A}/tip$ at the anode-to-cathode voltage of 25 V. These superior field emission characteristics was speculated as a result of strong surface modification inducing a quasi-negative electron affinity and the increase of emitting sites due to local sharp protrusions by an appropriate activation treatment. In respect, two kinds of procedures were proposed for the fabrication of the lateral type GaN emitter: a selective etching method with electron cyclotron resonance-reactive ion etching (ECR-RIE) or a simple selective growth by utilizing $Si_3N_4$ film as a masking layer. The fabricated device using the ECR-RIE exhibited electrical characteristics such as a turn-on voltage of 35 V for $7\bu\textrm{m}$ gap and an emission current of~580 nA/l0tips at anode-to-cathode voltage of 100 V. These new field emission characteristics of GaN tips are believed to be due to a low electron affinity as well as the shorter inter-electrode distance. Compared to lateral type GaN field emission diode using ECR-RIE, re-grown GaN emitters shows sharper shape tips and shorter inter-electrode distance.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.83-88
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• 2020

The evolution of smartphones has led to numerous researches in the mechanical behavior of flexible devices. Due to the nano-size of the thin flexible film, nanoindentation is widely used to evaluate its mechanical behaviors, such as elastic modulus, and hardness. However, the commonly used Oliver-Pharr method is not suited for analyzing the indentation force-depth curves of hard films on soft substrates, as the effects of soft substrate is not considered theoretically. In this study, the elastic modulus of the thin film was evaluated with references to other reported models which include the substrate effect, and with calibration of the indentation depth for the pile-ups between the indenter and test surface. We fabricated test samples by deposition of amorphous metal film on polyimide and silicon wafers for verification of modified models.

• Korean Journal of Materials Research
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• v.10 no.1
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• pp.21-28
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• 2000

Refractory metals, W and Ti, and their nitrides, $W_2N$ and TiN, were investigated for using as an ohmic contact material with SiC single crystalline thin films. The possibility of nitride materials for using as a stable ohmic contact material of SiC at high temperatures was examined by considering the thermal stability depending on the heat treatment temperature, their electrical properties and protective behavior from the interdiffusion. W contact with SiC thin films, deposited by using new organosilicon precursor, bis-trimethylsilylmethane, showed the lowest resistivity, $2.17{\times}10^{-5}$Ω$\textrm{cm}^2$. On the other hand, Ti-based contact materials showed higher contact resistivity than W-based ones. The oxidation of contact materials was restricted by applying Pt thin films on those electrodes. Nitride electrodes had rather stable electrical properties and better protective behavior from interdiffusion than metal electrodes.

• Journal of the Korea Institute of Military Science and Technology
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• v.1 no.1
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• pp.227-237
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• 1998

HgCdTe Is the most versatile material for the developing infrared devices. Not like III-V compound semiconductors or silicon-based photo-detecting materials, HgCdTe has unique characteristics such as adjustable bandgap, very high electron mobility, and large difference between electron and hole mobilities. Many research groups have been interested in this material since early 70's, but mainly due to its thermodynamic difficulties for preparing materials, no single growth technique is appreciated as a standard growth technique in this research field. Solid state recrystallization(SSR), travelling heater method(THM), and Bridgman growth are major techniques used to grow bulk HgCdTe material. Materials with high quality and purity can be grown using these bulk growth techniques, however, due to the large separation between solidus and liquidus line on the phase diagram, it is very difficult to grow large materials with minimun defects. Various epitaxial growth techniques were adopted to get large area HgCdTe and among them liquid phase epitaxy(LPE), metal organic chemical vapor deposition(MOCVD), and molecular beam epitaxy(MBE) are most frequently used techniques. There are also various types of photo-detectors utilizing HgCdTe materials, and photovoltaic and photoconductive devices are most interested types of detectors up to these days. For the larger may detectors, photovoltaic devices have some advantages over power-requiring photoconductive devices. In this paper we reported the main results on the HgCdTe growing and characterization including LPE and MOCVD, device fabrication and its characteristics such as single element and linear array($8{\times}1$ PC, $128{\times}1$ PV and 4120{\times}1$ PC). Also we included the results of the dewar manufacturing, assembling, and optical and environmental test of the detectors.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.267-274
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• 2005

This paper presents the fabrication of surface acoustic wave (SAW)-based pressure sensor for long-term stable mechanical compression force measurement. SAW pressure sensor has many attractive features for practical pressure measurement: no battery requirement, wireless pressure detection especially at hazardous environments, and easy other functionality integrations such as temperature, humidity, and RFID. A $41^{\circ}$ YX $LiNbO_3$ piezoelectric substrate was used because of its high SAW propagation velocity and large values of electromechanical coupling factors $K^2$. A silicon substrate with $\~200{\mu}m$ deep cavity was bonded to the diaphragm with epoxy, in which gold was covered all over the inner cavity in order to confine electromagnetic energy inside the sensor, and provide good isolation of the device from its environment. The reflection coefficient $S_{11}$ was measured using network analyzer. High S/N ratio, sharp reflected peaks, and clear separation between the peaks were observed. As a mechanical compression force was applied to the diaphragm from top with extremely sharp object, the diaphragm was bended, resulting in the phase shifts of the reflected peaks. The phase shifts were modulated depending on the amount of applied mechanical compression force. The measured $S_{11}$ results showed a good agreement with simulated results obtained from equivalent admittance circuit modeling.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.229-232
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• 2001

4H-SIC(silicon carbide) MESFET large signal model was studied using modified Materka-Kacprzak large signal MESFET model. 4H-SiC MESFET device simulation have been conducted by Silvaco's 2D device simulator, ATLAS. The result is modeled using modified Materka large signal model. simulation and modeling results are -8V pinch off voltage, under $V_{GS=0V}$, $V_{DS=25V}$ conditions, $I_{DSS=270㎃}$mm, $G_{m=45㎳}$mm were obtained. Through the power simulation 2GHz, at the bias of $V_{GS=-4V}$ and $V_{DS=25V}$, 10dB Gain, 34dBm(1dB compression point)output power, 7.6W/mm power density, 37% PAE(power added efficiency) were obtained.d.d.d.

• Journal of Sensor Science and Technology
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• v.20 no.3
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• pp.156-161
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• 2011

We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.163-163
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• 1999

MOSFET, MESFET 그리고 MODFET는 Logic ULSIs, high speed ICs, RF MMICs 등에서 중요한 역할을 하고 있으며, 그것의 gate electrode, contact, interconnect 등의 물질로는 refractory metal을 이용한 CoSi2, MoSi2, TaSi2, PtSi2, TiSi2 등의 효과를 얻어내고 있다. 그중 TiSi2는 비저항이 가장 낮고, 열적 안정도가 좋으며 SAG process가 가능하므로 simpler alignment process, higher transconductance, lower source resistance 등의 장점을 동시에 만족시키고 있다. 최근 소자차원이 scale down 됨에 따라 TiSi2의 silicidation 과정에서 C49 TiSi2 phase(high resistivity, thermally unstable phase, larger grain size, base centered orthorhombic structure)의 출현과 그것을 제거하기 위한 노력이 큰 issue로 떠오르고 있다. 여러 연구 결과에 따르면 PAI(Pre-amorphization zimplantation), HTS(High Temperature Sputtering) process, Mo(Molybedenum) implasntation 등이 C49를 bypass시키고 C54 TiSi2 phase(lowest resistivity, thermally stable phase, smaller grain size, face centered orthorhombic structure)로의 transformation temperature를 줄일 수 있는 가장 효과적인 방법으로 제안되고 있지만, 아직 그 문제가 완전히 해결되지 않은 상태이며 C54 nucleation에 대한 physical mechanism을 밝히진 못하고 있다. 본 연구에서는 증착 시 기판온도의 변화(400~75$0^{\circ}C$)에 따라 silicon 위에 DC/RF magnetron sputtering 방식으로 Ti/Si film을 각각 제작하였다. 제작된 시료는 N2 분위기에서 30~120초 동안 500~85$0^{\circ}C$의 온도변화에 따라 RTA법으로 각각 one step annealing 하였다. 또한 Al을 cosputtering함으로써 Al impurity의 존재에 따른 영향을 동시에 고려해 보았다. 제작된 시료의 분석을 위해 phase transformation을 XRD로, microstructure를 TEM으로, surface topography는 SEM으로, surface microroughness는 AFM으로 측정하였으며 sheet resistance는 4-point probe로 측정하였다. 분석된 결과를 보면, 고온에서 제작된 박막에서의 C54 phase transformation temperature가 감소하는 것이 관측되었으며, Al impuritydmlwhswork 낮은온도에서의 C54 TiSi2 형성을 돕는다는 것을 알 수 있었다. 본 연구에서는 결론적으로, 고온에서 증착된 박막으로부터 열적으로 안정된 phase의 낮은 resistivity를 갖는 C54 TiSi2 형성을 보다 낮은 온도에서 one-step RTA를 통해 얻을 수 있다는 결과와 Al impurity가 존재함으로써 얻어지는 thermal budget의 효과, 그리고 그로부터 기대할 수 있는 여러 장점들을 보고하고자 한다.

• Journal of the Korean Ceramic Society
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• v.35 no.2
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• pp.172-179
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• 1998

Valve lifter namely tappet is supported by lifter hole which is located upper side of camshaft in cylinder block transforms rotatic mvement of camshaft into linear movement and helps to open and shut the en-gine valve as an engine parts. The face of valve lifter which is continuously contacting with camshaft brings about abnormal wears such as unfair wear and early wear because it is severely loaded in the valve train system. These wears act as a defect like over-clearance and cause imperfect combustion of fuel during the valve lifting in the combustion chamber. Consequently this imperfect combustion makes the engine out-put decrease and has cause on air pollution. To prevent these wears therefore The valve lifter cast in me-tal developed into SiC ceramics valve lifter which has an excellence in wear and impact resistance As a results the optimum process conditions like injection condition mixture ratio and debonding process could be established. After sintering fine-sinered dual microstructure in which prior ${\alpha}$-SiC matches well with new SiC(${\beta}$-SiC) produced by reaction among the ${\alpha}$-SiC carbon and silicon was obtained. Based on the study it is verified that mechanical properties of SiC valve lifter are excellent in Vickers hardness 1100-1200 bending strength (300-350 Pa) fracture toughness(1.5-1.7 Mpa$.$m1/2) Through engine dynamo test-ing SiC valve lifter and metal valve lifter are examined and compared into abnormal phenomena such as early fracture unfair and early wear. It is hoped that this research will serve as an important springboard for the future study of heavy duty diesel engine parts developed by ceramics which has a good wear resis-tance relaibility and lightability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.35-40
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• 2005

A digitally controlled phase-locked loop (DCPLL) is described. The DCPLL has basically the same structure as a conventional analog PLL except for a tracking analog-to-digital converter (ADC). The tracking ADC generates the control signal for voltage controlled oscillator. Since the DCPLL employs neither digitally controlled oscillator nor time-to-digital converter-the key building blocks of digital PLL (DPLL), there is no need for the 03de-off between jitter, power consumption and silicon area. The DCPLL was implemented in a $0.18\mu$m CMOS process and the active area is 1mm $\times$0.35 mm The DCPLL consumes S9mW during the normal opuation and $984\{mu}W$ during the power-down mode from a 1.8V supply. The DCPLL shows 16.8ps ms jitter.