• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.39 no.4
• /
• pp.16-24
• /
• 2002

This work describes a 10b 120 MSample/s CMOS pipelined A/D converter(ADC) based on a merged-capacitor switching(MCS) technique for high signal processing speed and high resolution. The proposed ADC adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area, and employs a MCS technique which improves sampling rate and resolution reducing the number of unit capacitor used in the multiplying digital-to-analog converter (MDAC). The proposed ADC is designed and implemented in a 0.25 um double-poly five-metal n-well CMOS technology. The measured differential and integral nonlinearities are within ${\pm}$0.40 LSB and ${\pm}$0.48 LSB, respectively. The prototype silicon exhibits the signal-to-noise-and-distortion ratio(SNDR) of 58 dB and 53 dB at 100 MSample/s and 120 MSample/s, respectively. The ADC maintains SNDR over 54 dB and the spurious-free dynamic range(SFDR) over 68 dB for input frequencies up to the Nyquist frequency at 100 MSample/s. The active chip area is 3.6 $mm^2$(＝ 1.8 mm ${\times}$ 2.0 mm) and the chip consumes 208 mW at 120 MSample/s.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.1
• /
• pp.60-68
• /
• 2010

In case of sensorineural hearing loss, auditory perception can be activated by electrical stimulation of the nervous system via electrode implanted into the cochlea or auditory nerve. Since the tonotopic map of the human auditory nerve has not been definitively identified, the recording of auditory nerve signal with microelectrode is desirable for determining the tonotopic map. This paper proposes the multi-channel analog front-end for auditory nerve signal detection. A channel of the proposed analog front-end consists of an AC coupling circuit, a low-power 4th-order Gm-C LPF, and a single-slope ADC. The AC coupling circuit transfers only AC signal while it blocks DC signal level. Considering the bandwidth of the auditory signal, the Gm-C LPF is designed with OTAs adopting floating-gate technique. For the channel-parallel ADC structure, the single-slope ADC is used because it occupies the small silicon area. Experimental results shows that the AC coupling circuit and LPF have the bandwidth of 100 Hz - 6.95 kHz and the ADC has the effective resolution of 7.7 bits. The power consumption per a channel is $12\;{\mu}W$, the power supply is 3.0 V, and the core area is $2.6\;mm\;{\times}\;3.7\;mm$. The proposed analog front-end was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.10
• /
• pp.6611-6617
• /
• 2015

The purpose of this study is to compare the marginal and internal fit of metal and zirconia coping which is fabricated by manual and CAD/CAM(Computer Aided Design/Computer Aided Manufacturing). The model is prepared with Urethane material and two abutment teeth are fabricated with a knife and chamfer margin. Silicon replica technique is used to measure the marginal fit of manually fabricated and the CAD/CAM coping. Internal fitting level is measured with a microscope and the image is captured with a CCD camera. The distance between abutment teeth and coping is measured with a callibrated image analyzer software; marginal opening (MO), marginal gap (MG), internal gap (IG) at maximum curvature area, axial gap (AG), and occlusal gap (OG). Two-way ANOVA test is applied to compare fabrication technique and to analysis of abutment pattern. In addition, one-way ANOVA and Scheffe's test is used to analyze each parameter of the test. The result shows that the fit is < $120{\mu}m$ except OG of CAD/CAM and MO of knife margin. The CAD/CAM fabricated coping showed higher fit level at chamfer margin. However, knife margin showed better fitness compared to chamfer margin at MG. AG showed the minimum dimension with a constant result (< $38{\mu}m$).

• Proceedings of the SAREK Conference
• /
• 2008.11a
• /
• pp.170-174
• /
• 2008

Recently, a problem related to the thermal management in portable electronic and telecommunication devices is becoming issued. That is due to the trend of slimness of the devices, so it is not easy to find the optimal thermal management technology for the devices. From now on, a pressed circular type cooling device has been mainly used, however the cooling device with thin thickness is becoming needed by the inner space constraint. In the present study, the silicon and metal flat plate type cooling device with the separated vapor and liquid flow path was designed and fabricated. Through the experimental study, the normal isothermal characteristic by vapor-liquid phase change was confirmed and the cooling device with 70mm of total length showed 6.8W of the heat transfer rate within the range of $4{\sim}5^{\circ}C$/W of thermal resistance. In the meantime, the metal cooling device was developed for commercialization. The device was designed to have all structures of evaporator, vapor flow path, liquid flow path and condenser in one plate. And an envelope of that could be completed by combining the two plates of same structure and size. And the simplicity of fabrication process and reduction of manufacturing cost could be accomplished by using the stamping technology for fabricating large flow paths relatively. In the future, it will be possible to develop the commercialized cooling device by revising the fabrication process and enhancing the thermal performance of that.

• Resources Recycling
• /
• v.29 no.2
• /
• pp.69-77
• /
• 2020

With rapid increasing production and installation, recycling of photovoltaic modules has become the main issue. According to the research, the accumulation of waste modules will reach to 8600 tons in 2030. Moreover, Crystalline-silicon (c-Si) Photovoltaic modules account for more than 90% of the waste. C-Si PV modules contain 1.3% of weight of photovoltaic ribbon inside which contains the most of lead, tin and copper in the PV modules, which would cause environmental and humility problem. This study provided a valuable metal separation process for PV ribbons. Ribbons content 82.1% of Cu, 8.9% of Sn, 5.2% of Pb, and 3.1% of Ag. All of them were leached by 3M of hydrochloric acid in the optimal condition. Ag was halogenated to AgCl and precipitated. Cu ion was extracted and separated from Pb and Sn by Lix984N then stripped by 3M H2SO4. The effect of the optimal parameters of extraction was also studied in this essay. The maximum extraction efficiency of Cu ion was 99.64%. The separation condition of Pb and Sn were obtained by adjusting the pH value to 4 thought ammonia to precipitate and separate Pb and Sn. The recovery of Pb and Sn can reach 99%.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.32 no.2
• /
• pp.55-60
• /
• 2022

In this study, a heat treatment experiment was conducted to select a new melt composition that can easily control the unintentionally doped nitrogen (N-UID) without degrading the SiC single crystal quality during TSSG process. The experiment was carried out for about 2 hours at a temperature of 1900℃ under Ar atmosphere. The used melt composition is based on either Si-Ti 10 at% or Si-Cr 30 at%, and also Co or Sc transition metals, which are effective for carbon solubility, were added at 3 at%, respectively. After the experiment, the crucible was cross-sectionally cut, and evaluated the Si-C reaction layer on the crucible-melt interface. As a result, with Sc addition, Si-C reaction layers uniformly occurred with a Si-infiltrated layer (~550 ㎛) and a SiC interlayer (~23 ㎛). This result represented that the addition of Sc is an effective transition metal with high carbon solubility and can feed carbon sources into the melt homogeneously. In addition, Sc is well known to have low reactivity energy with nitrogen compared to other transition metals. Therefore, we expect that both growth rate and Nitrogen UID can be controlled by Si-Sc based melt in the TSSG process.

• Proceedings of the KIEE Conference
• /
• 1999.07d
• /
• pp.1504-1507
• /
• 1999

We have grown vertically aligned carbon nanotubes in a large area of Co-Ni codeposited Si substrates by the thermal CVD using $C_2H_2$ gas. Since the discovery of carbon nanotubes, Synthesis of carbon nanotubes for mass production has been achieved by several methods such as laser vaporization arc discharge, and pyrolysis. In particular, growth of vertically aligned nanotubes is of technological importance for applications to FED. Recently, vertically aligned carbon nanotubes have been grown on glass by PECVD Aligned carbon nanotubes can be also grown on mesoporous silica and Fe patterned porous silicon using CVD. Despite such breakthroughs in the growth, the growth mechanism of the alignment are still far from being clearly understood. Furthermore, FED has not been clearly demonstrated yet at a practical level. Here, we demonstrate that carbon nanotubes can be vertically aligned on catalyzed Si substrate when the domain density reaches a certain value. We suggest that steric hindrance between nanotubes at an initial stage of the growth forces nanotubes to align vertically and then nanotubes are further grown by the cap growth mechanism.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.13 no.2
• /
• pp.808-816
• /
• 2012

This paper is the study for the directional solidification of the ingot through the thermal analysis simulation and structural change of casting furnace. With the results of thermal analysis simulation, the silicon as a whole has reached the melting temperature as the retention time 80 min. The best cooling conditions showed at the upper cooling temperature $1,400^{\circ}C$ and cooling time 60min. The fabricated wafers showed the superior etching result at the grain boundary than that of existing commercial wafers. The FTIR measurements of oxygen and carbon impurities were not in the critical value for solar conversion efficiency. The NAA analysis of metal impurities were also detected the total number of 18 different metals, but the concentration distribution showed no significant positional deviations in the same position from the top to the bottom.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.108-109
• /
• 2012

This talk will begin with the demonstration of facile synthesis of silicon nanostructures using the magnesiothermic reduction on silica nanostructures prepared via self-assembly, which will be followed by the characterization results of their performance for energy storage. This talk will also report the fabrication and characterization of highly porous, stretchable, and conductive polymer nanocomposites embedded with carbon nanotubes (CNTs) for application in flexible lithium-ion batteries. It will be presented that the porous CNT-embedded PDMS nanocomposites are capable of good electrochemical performance with mechanical flexibility, suggesting these nanocomposites could be outstanding anode candidates for use in flexible lithium-ion batteries. Directed self-assembly (DSA) of block copolymers (BCPs) can generate uniform and periodic patterns within guiding templates, and has been one of the promising nanofabrication methodologies for resolving the resolution limit of optical lithography. BCP self-assembly processing is scalable and of low cost, and is well-suited for integration with existing semiconductor manufacturing techniques. This talk will introduce recent research results (of my research group) on the self-assembly of Si-containing block copolymers for the achievement of sub-10 nm resolution, fast pattern generation, transfer-printing capability onto nonplanar substrates, and device applications for nonvolatile memories. An extraordinarily facile nanofabrication approach that enables sub-10 nm resolutions through the synergic combination of nanotransfer printing (nTP) and DSA of block copolymers is also introduced. This simple printing method can be applied on oxides, metals, polymers, and non-planar substrates without pretreatments. This talk will also report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by the self-assembly of Si-containing BCPs. This approach offers a practical pathway to fabricate high-density resistive memory devices without using high-cost lithography and pattern-transfer processes. Finally, this talk will present a novel approach that can relieve the power consumption issue of phase-change memories by incorporating a thin $SiO_x$ layer formed by BCP self-assembly, which locally blocks the contact between a heater electrode and a phase-change material and reduces the phase-change volume. The writing current decreases by 5 times (corresponding to a power reduction of 1/20) as the occupying area fraction of $SiO_x$ nanostructures varies.

• Journal of the Korean Society for Nondestructive Testing
• /
• v.18 no.2
• /
• pp.112-120
• /
• 1998

A nondestructive evaluation technique was developed for the quantitative determination of the reinforcement volume fractions in particulate reinforced metal matrix composites. The proposed technique employed a composite micromechanics which accounts for the microstructure of the composite medium together with the measurement of anisotropic electrical conductivity. When the measured conductivity was coupled with the theoretically predicted conductivity, the unknown reinforcement volume fraction was calculated. An analytical model based on the Mori-Tanaka method was described which relates the NDE signatures to the composite microstructure. The volume fractions were calculated using eddy current measurements made on a wide range of silicon carbide particulate ($SiC_p$) reinforced aluminum (Al) matrix composites. The calculated $SiC_p$ volume fractions were in good agreement with the measured volume fractions in the range of 0-30%. The technique was also found to be effective in estimating the total volume percentage of reinforcement and intermetallic compound formed during the processing stage.