• 전기학회논문지
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• 제59권8호
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• pp.1406-1415
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• 2010

As process technology for semiconductor goes beyond the ultra-deep submicrometer regime, interconnect reliability on a chip has become a serious design concern. As process parameters scale, interconnect widths are reduced rapidly while the current flowing through the interconnect does not decrease in a proportional manner. This trend increases current densities in metal interconnects which may lead to poor reliability for electromigration. Hence, it is critical to estimate the current amount passing through the interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast yet accurate current estimation technique that can offer not only analysis time equivalent to those offered by the previous approximation methods but also a relatively precise estimation by using closed-form equations. The accuracy of the proposed technique was confirmed to be about 8 times better on average when compared to the previous work.

• 한국결정학회지
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• 제16권2호
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• pp.89-101
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• 2005

Among many material processing related issues for successful scaling down of devices for the next 10 years or so, the advanced gate stack and interconnect technology are two most critical research areas, which need technical innovation. The introduction of new metallic films and appropriate processing technologies are required more than ever. Especially, as the device downscaling continues well into sub 50 nm regime, the paradigm for metal nano film deposition technique research has been shifted to high conformality, low growth temperature, high quality with uniformity at large area wafers. Regarding these, ALD has sparked a lot of interests for a number of reasons. The process is intrinsically atomic in nature, resulting in the controlled deposition of films in sub-monolayer units with excellent conformality. In this paper, the overview on the current issues and the future trends in device processing technologies related to metal nano films as well as the R&D trends in these applications will be discussed. The focus will be on the applications for metal gate, capacitor electrode for DRAM, and diffusion barriers/seed layers for Cu interconnect technology.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.244.1-244.1
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• 2016

Recently, the technology for flexible electronics such as flexible smart phone, foldable displays, and bendable battery is under active development. With approaching the real commercialization of flexible electronics, the electrical and mechanical reliability of flexible electronics have become significantly important because they will be used under various mechanical deformations such as bending, twisting, stretching, and so on. These mechanical deformations result in performance degradation of electronic devices due to several mechanical problems such as cracking, delamination, and fatigue. Therefore, the understanding of relationship between mechanical loading and electrical performance is one of the most critical issues in flexible electronics for expecting the lifetime of products. Here, we have investigated the effect of monotonic tensile and cyclic deformations on metal interconnect to provide a guideline for improving the reliability of flexible interconnect.

• KEPCO Journal on Electric Power and Energy
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• 제5권2호
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• pp.121-125
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• 2019

A YSZ electrolyte based ceramic supported Solid Oxide Cell (SOC) and a metal interconnect supported SOC was investigated under both fuel cell and co-electrolysis (steam and $CO_2$) mode at $800^{\circ}C$. The single cell performance was analyzed by impedance spectra and product gas composition with gas chromatography(GC). The long-term performance in the co-electrolysis mode under a current density of $800mA/cm^2$ was obtained using steam and carbon dioxide ($CO_2$) mixed gas condition.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Corrosion Science and Technology
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• 제6권1호
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• pp.1-6
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• 2007

Ferritic stainless steels for the SOFC interconnect applications are required to possess not only a good oxidation resistance, but also a high electrical conductivity of the oxide scale that forms during exposure at the SOFC operating environment. In order to understand the effects of alloying elements on the oxidation behavior of ferritic stainless steels and on the electrical properties of oxide scales, two kinds of commercial ferritic stainless steels, STS 430 and STS 444, were investigated by performing isothermal oxidations at $800^{\circ}C$ in a wet air containing 3% $H_{2}O$. The results showed that STS 444 was superior to STS 430 in both of the oxidation resistance and the area specific resistance. Although STS 444 contained a less amount of Mn for the $(Mn,Cr)_{3}O_{4}$ spinel formation than STS 430, the minor alloying elements of Al and Mo in STS 444, which were accumulated in the base metal region adjacent the scale, were suggested to reduce the scale growth rate and to enhance the scale adherence to the base metal.

• 전기학회논문지
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• 제60권8호
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• pp.1547-1554
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• 2011

As process parameters scale, interconnect width are reduced rapidly while the current flowing through interconnects does not decrease in a proportional manner. This effect increases current density in metal interconnects which may result in poor reliability. Since RMS(root-mean-square) current limits are used to evaluate self-heating and short-time stress failures caused by high-current pluses, RMS current estimation is very important to guarantee the reliability of semiconductor systems. Hence, it is critical to estimate the current limits through interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast, yet accurate RMS current estimation technique that can offer a relatively precise estimate by using closed-form equations. The efficiency and accuracy of the proposed method have been verified through simulations using HSPICE for a vast range of interconnect parameters.

• 전자공학회논문지D
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• 제36D권5호
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• pp.44-53
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• 1999

본 논문에서는 반도체 집적 회로의 다층 배선 인터커넥트 사이의 기생 캐패시턴스를 수치 해석적으로 계산하여 추출하는 새로운 방법과 그 적용 예를 보고한다. 기생 캐패시턴스를 시뮬레이션을 통해 추출하기 위하여, 복잡한 형태의 3차원 대층배선 구조물을 유한요소법을 이용하여 해석하였다. 캐패시턴스를 추출하기 위한 3차원 다층배선 구조물은 3차원 변환 정보를 가진 2차원 평면 마스크 레이아웃 데이터로부터 생성하였다. 시뮬레이션 결과의 정확도를 검증을 위하여 8.0×8.0×5.0㎛\sup 3\ 크기의 영역에 평행한 두 도전층이 상하로 교차한 구조에 대하여 실험치와 비교하였다. 3차원 다층배선 구조물의 기생 캐패시턴스 추출을 위해서, 유한 요소법 적용을 위한 1,960개의 노드와 8,892개의 사면체 메쉬를 생성하였으며, ULTRA SPARC 1 워크스테이션에 대해서 소요된 CPU 시간은 28초이었으며, 4.4 메가바이트의 메모리를 사용하였다.

• 대한전자공학회논문지SD
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• 제41권4호
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• pp.101-112
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• 2004

본 논문에서는 3차원 인터커넥트(3D interconnect) 구조를 해석하기 위하여 ADI-유한차분시간영역(ADI-FDTD: Alternating Direction Implicit Finite Difference Time Domain)법으로 맥스웰 회전 방정식(Maxwell's curl equation)을 계산하는 수치 해석 모델을 개발하였고, 개발한 ADI-유한차분시간영역법을 이용하여 3.3 V CMOS 기술로 설계된 샘플러 회로의 일부의 영역에 대해 컴퓨터 모의 실험 결과하여 입력된 구형 전압 신호가 금속 배선을 거치면서 5∼10 ps의 신호 지연과 0.1∼0.2 V의 신호 왜곡이 발생되는 것을 확인하였다. 결론적으로 ADI-유한차분시간영역법을 이용한 풀-웨이브 해석을 통하여 고속의 VLSI 인터커넥트에서의 전자기 현상을 정확하게 분석할 수 있음을 제시하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권3호
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.