• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.8
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• pp.1406-1415
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• 2010

As process technology for semiconductor goes beyond the ultra-deep submicrometer regime, interconnect reliability on a chip has become a serious design concern. As process parameters scale, interconnect widths are reduced rapidly while the current flowing through the interconnect does not decrease in a proportional manner. This trend increases current densities in metal interconnects which may lead to poor reliability for electromigration. Hence, it is critical to estimate the current amount passing through the interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast yet accurate current estimation technique that can offer not only analysis time equivalent to those offered by the previous approximation methods but also a relatively precise estimation by using closed-form equations. The accuracy of the proposed technique was confirmed to be about 8 times better on average when compared to the previous work.

• Korean Journal of Crystallography
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• v.16 no.2
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• pp.89-101
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• 2005

Among many material processing related issues for successful scaling down of devices for the next 10 years or so, the advanced gate stack and interconnect technology are two most critical research areas, which need technical innovation. The introduction of new metallic films and appropriate processing technologies are required more than ever. Especially, as the device downscaling continues well into sub 50 nm regime, the paradigm for metal nano film deposition technique research has been shifted to high conformality, low growth temperature, high quality with uniformity at large area wafers. Regarding these, ALD has sparked a lot of interests for a number of reasons. The process is intrinsically atomic in nature, resulting in the controlled deposition of films in sub-monolayer units with excellent conformality. In this paper, the overview on the current issues and the future trends in device processing technologies related to metal nano films as well as the R&D trends in these applications will be discussed. The focus will be on the applications for metal gate, capacitor electrode for DRAM, and diffusion barriers/seed layers for Cu interconnect technology.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.244.1-244.1
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• 2016

Recently, the technology for flexible electronics such as flexible smart phone, foldable displays, and bendable battery is under active development. With approaching the real commercialization of flexible electronics, the electrical and mechanical reliability of flexible electronics have become significantly important because they will be used under various mechanical deformations such as bending, twisting, stretching, and so on. These mechanical deformations result in performance degradation of electronic devices due to several mechanical problems such as cracking, delamination, and fatigue. Therefore, the understanding of relationship between mechanical loading and electrical performance is one of the most critical issues in flexible electronics for expecting the lifetime of products. Here, we have investigated the effect of monotonic tensile and cyclic deformations on metal interconnect to provide a guideline for improving the reliability of flexible interconnect.

• KEPCO Journal on Electric Power and Energy
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• v.5 no.2
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• pp.121-125
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• 2019

A YSZ electrolyte based ceramic supported Solid Oxide Cell (SOC) and a metal interconnect supported SOC was investigated under both fuel cell and co-electrolysis (steam and $CO_2$) mode at $800^{\circ}C$. The single cell performance was analyzed by impedance spectra and product gas composition with gas chromatography(GC). The long-term performance in the co-electrolysis mode under a current density of $800mA/cm^2$ was obtained using steam and carbon dioxide ($CO_2$) mixed gas condition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Corrosion Science and Technology
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• v.6 no.1
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• pp.1-6
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• 2007

Ferritic stainless steels for the SOFC interconnect applications are required to possess not only a good oxidation resistance, but also a high electrical conductivity of the oxide scale that forms during exposure at the SOFC operating environment. In order to understand the effects of alloying elements on the oxidation behavior of ferritic stainless steels and on the electrical properties of oxide scales, two kinds of commercial ferritic stainless steels, STS 430 and STS 444, were investigated by performing isothermal oxidations at $800^{\circ}C$ in a wet air containing 3% $H_{2}O$. The results showed that STS 444 was superior to STS 430 in both of the oxidation resistance and the area specific resistance. Although STS 444 contained a less amount of Mn for the $(Mn,Cr)_{3}O_{4}$ spinel formation than STS 430, the minor alloying elements of Al and Mo in STS 444, which were accumulated in the base metal region adjacent the scale, were suggested to reduce the scale growth rate and to enhance the scale adherence to the base metal.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.8
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• pp.1547-1554
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• 2011

As process parameters scale, interconnect width are reduced rapidly while the current flowing through interconnects does not decrease in a proportional manner. This effect increases current density in metal interconnects which may result in poor reliability. Since RMS(root-mean-square) current limits are used to evaluate self-heating and short-time stress failures caused by high-current pluses, RMS current estimation is very important to guarantee the reliability of semiconductor systems. Hence, it is critical to estimate the current limits through interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast, yet accurate RMS current estimation technique that can offer a relatively precise estimate by using closed-form equations. The efficiency and accuracy of the proposed method have been verified through simulations using HSPICE for a vast range of interconnect parameters.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.101-112
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• 2004

In this paper, we developed a numerical analysis model by using ADI-FDTD method to analyze three-dimensional interconnect structure. We discretized maxwell's curl equation by using ADI-FDTD. Using ADI-FDTD method, a sampler circuit designed from 3.3 V CMOS technology is simplified to 3-metal line structure. Using this simplified structure, the time delay and signal distortion of complex interconnects are investigated. As results of simulation, 5∼10 ps of delay time and 0.1∼0.2 V of signal distortion are measured. As demonstrated in this paper, the full-wave analysis using ADI-FDTD exhibits a promise for accurate modeling of electromagnetic phenomena in high-speed VLSI interconnect.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.3
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• pp.189-192
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• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.