• Journal of Information Display
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• v.13 no.2
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• pp.61-66
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• 2012

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at $350^{\circ}C$. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2011.05a
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• pp.115-115
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• 2011

고성능 금속 커패시터 개발을 목적으로 aluminum film에 균일한 etch fit를 형성하는 연구를 진행하였다. Etch mask로 PI를 사용하여 Aluminum film에 균일한 형태의 etch fit를 형성하였다. 균일하게 에칭 된 aluminum film들은 capacitance를 측정하여 에칭 조건에 따른 capacitance 변화를 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05b
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• pp.74-77
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• 2002

Ferroelectric Random Access Memory(FRAM) and MEMS applications require noble metal or refractory metal oxide electrodes. In this study, Ru thin films were etched using $O_2$+10% $CF_4$ plasma in an inductively coupled plasma(ICP) etching system. The etch rate of Ru thin films was examined as function of rf power, DC bias applied to the substrate. The enhanced etch rate can be obtained not only with increasing rf power and DC bias voltage, but also with small addition $CF_4$ gas. The selectivity of $SiO_2$ over Ru are 1.3. Radical densities of oxygen and fluorine in $CF_4/O_2$ plasma have been investigated by optical emission spectroscopy(OES). The etching profiles of Ru films with an photoresist pattern were measured by a field emission scanning electron microscope (FE-SEM). The additive gas increases the concentration of oxygen radicals, therefore increases the etch rate of the Ru thin films and enhances the etch slope. In $O_2$+10% $CF_4$ plasma, the etch rate of Ru thin films increases up to 10% $CF_4$ but decreases with increasing $CF_4$ mixing ratio.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.410-414
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• 2013

We report the wet etching of titanium nickel (TiNi) films for the production of nano-electro-mechanical (NEM) device. $SiO_2$ and $Si_3N_4$ have been selected as sacrificial layers of TiNi metal and etched with polyethylene glycol and hydrofluoric acid (HF) mixed solution. Volume percentage of HF are varied from 10% to 35% and the etch rate of the $SiO_2$, $Si_3N_4$ and TiNi are reported here. Within the various experiment results, 15% HF mixed polyethylene glycol solution show highest etch ratio between sacrificial layer and TiNi metal. Especially $Si_3N_4$ films shows high etch ratio with TiNi films. Wet etching results are measured with SEM inspection. Therefore, this experiment provides a novel method for TiNi in the nano-electro-mechanical device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11b
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.4
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• pp.327-331
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• 2008

An in-line wet etch/cleaning system was established for the research and development in wet etch process as a formation of electrode such as metal or transparent conductive oxide layer. A reverse moving system was equipped in the in-line wet etch/cleaning system for the alternating motion of glass substrate in a wet etch bath of the system. Therefore, it was possible for the glass substrate to be moved back and forth and it was possible to reduce the size of the system by using the reversing moving system. For the effect of the alternating motion of substrate on the etch rate in the in-line wet etch bath, indium tin oxide(ITO) patterns were obtained through wet etch process in the in-line system in which the substrate was moved back and forth. From the CD(critical dimension) skews resulted from the ADI CD and ACI CD of the ITO patterns, it was concluded that the alternating motion of glass substrate are possible to be applied to the mass production of wet etch process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2525-2531
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• 2012

Al-Cu alloy has been used as a circuit material for its low resistance and ease to process for long years at CMOS technology. However, basically metal is very susceptible to corrosion and which has been a long pending trouble in various fields using metal. The defect causes the reliability concerns, so improved methods are necessary to reduce the defect. In the various corrosion parameters, PR strip process conditions after metal etch and optimal cleaning solutions are controllable and increase the process margin to prevent the metal corrosion. This study proposes that chlorine residue after metal etch as the source of metal corrosion, and charges should be removed by optimizing PR strip process condition and cleaning condition.

• The Journal of Advanced Prosthodontics
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• v.8 no.5
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• pp.339-344
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• 2016

PURPOSE. Pre-surface treatments of coping materials have been recommended to enhance the bonding to the veneering ceramic. Little is known on the effect on shear bond strength, particularly with new coping material. The aim of this study was to investigate the shear bond strength of veneering ceramic to three coping materials: i) metal alloy (MA), ii) zirconia oxide (ZO), and iii) lithium disilicate (LD) after various pre-surface treatments. MATERIALS AND METHODS. Thirty-two (n = 32) discs were prepared for each coping material. Four pre-surface treatments were prepared for each sub-group (n = 8); a) no treatment or control (C), b) sandblast (SB), c) acid etch (AE), and d) sandblast and acid etch (SBAE). Veneering ceramics were applied to all discs. Shear bond strength was measured with a universal testing machine. Data were analyzed with two-way ANOVA and Tukey's multiple comparisons tests. RESULTS. Mean shear bond strengths were obtained for MA ($19.00{\pm}6.39MPa$), ZO ($24.45{\pm}5.14MPa$) and LD ($13.62{\pm}5.12MPa$). There were statistically significant differences in types of coping material and various pre-surface treatments (P<.05). There was a significant correlation between coping materials and pre-surface treatment to the shear bond strength (P<.05). CONCLUSION. Shear bond strength of veneering ceramic to zirconia oxide was higher than metal alloy and lithium disilicate. The highest shear bond strengths were obtained in sandblast and acid etch treatment for zirconia oxide and lithium disilicate groups, and in acid etch treatment for metal alloy group.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.