• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.661-674
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• 2000

The main memory DBMS(MMDBMS) efficiently supports various database applications that require high performance since it employs main memory rather than disk as a primary storage. In this paper, we discuss theexperiences obtained in developing the index manager of the Tachyon, a next-generation MMDBMS. The indexmanager is an essential sub-component of the DBMS used to speed up the retrieval of objects from a largevolume of a database in response to a certain search condition. Previous research efforts on indexing proposed various index structures. However, they hardly dealt with the practical issues occured in implementating an index manager on a target DBMS. In this paper, we touch these issues and present our experiences in developing the index manager on the Tachyon as solutions. The main issues touched are (1) compact representation of an indexentry, (2) support of variable-length keys, (3) support of multiple-attribute keys, (4) support of duplicated keys,(5) definition of external APls, (6) concurrency control, and (7) backup and recovery. We believe that ourcontribution would help MMDBMS developers highly reduce their trial-and-errors.

• The KIPS Transactions:PartA
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• v.13A no.5 s.102
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• pp.413-420
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• 2006

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• Journal of Korea Game Society
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• v.14 no.6
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• pp.59-68
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• 2014

Memory bandwidth requirements of UHD (Ultra High Definition $4096{\times}2160$) game scenes have been much more increasing. This paper presents a lossless DPCM-GR based compression algorithm using CUDA for solving the memory bandwidth problem without sacrificing image quality, which is modified from DDPCM-GR [4] to support bit parallel pipelining. The memory bandwidth efficiency increases because of using the shared memory of CUDA. Various asynchronous transfer configurations which can overlap the kernel execution and data transfer between host and CUDA are implemented with the page-locked host memory. Experimental results show that the maximum 31.3 speedup is obtained according to CPU time. The maximum 30.3% decreases in the computation time among various configurations.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.6
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• pp.477-487
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• 2005

As embedded system grows in size and complexity, the importance of the technique for dynamic memory allocation has increased. The objective of this paper is to measure the performance of dynamic memory allocation by varying both hardware and software design parameters for embedded systems. Unlike torrent performance evaluation studies that have presumed the single threaded system with single address spate without OS support, our study adopts realistic environment where the embedded system runs on Linux OS. This paper contains the experimental performance analyses of dynamic memory allocation method by investigating the effects of each software layer and some hardware design parameters. Our quantitative results tan be used to help system designers design high performance, low power embedded systems.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.3
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• pp.13-18
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• 2023

As the number of mobile applications increases rapidly, the overhead of swapping in smartphone memory systems keeps increasing. Unlike desktop or server systems, the basic setting of smartphones does not support swapping, so applications are killed when available memory is exhausted. This is because swapping in smartphones incurs excessive storage I/O overhead. In this article, we propose a swapping policy for smartphones, which significantly reduces storage I/Os. The proposed policy categorizes mobile applications based on their functional characteristics, and controls the number of applications to be swapped based on application priorities and memory situations. Measurement experiments with Android reference devices show that the proposed swapping policy dramatically reduces the overhead of swapping in various mobile applications.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.3
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• pp.136-142
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• 2006

Existing buffer management schemes for shared-memory output queueing switches can be classified into two types: In the first type, some constant amount of memory space is guaranteed to each virtual queue using static queue thresholds. The static threshold method (ST) belongs to this type. On the other hand, the second type of approach tries to maximize the buffer utilization in 머 locating buffer memories. The complete sharing (CS) method is classified into this type. In the case of CS, it is very hard to protect regular traffic from mis-behaving traffic flows while in the case of ST the thresholds can not be adjusted according to varying traffic conditions. In this paper, we propose a new buffer management method called weighted dynamic thresholds (WDT) which can process packet flows based on loss priorities for quality-of-service (QoS) functionalities with fairly high memory utilization factors. We verified the performance of the proposed scheme through computer simulations.

• KIISE Transactions on Computing Practices
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• v.23 no.8
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• pp.466-472
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• 2017

Hardware Transactional Memory (HTM) has greatly changed the parallel programming paradigm for transaction processing. Since Intel has recently proposed Transactional Synchronization Extension (TSX), a number of studies based on HTM have been conducted. However, the existing studies support conflict prediction for a single cause of the transaction processing and provide a standardized TSX environment for all workloads. To solve the problems, we propose an efficient hardware transactional memory scheme for processing transactions in multi-core in-memory environment. First, the proposed scheme determines whether to use Software Transactional Memory (STM) or the serial execution as a fallback path of HTM by using a prediction matrix to collect the information of previously executed transactions. Second, the proposed scheme performs efficient transaction processing according to the characteristic of a given workload by providing a retry policy based on machine learning algorithms. Finally, through the experimental performance evaluation using Stanford transactional applications for multi-processing (STAMP), the proposed scheme shows 10~20% better performance than the existing schemes.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.5
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• pp.41-49
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• 2010

Being popularized the use of portable entertainment/information devices, the demand on flash memory has been also increased radically. In general, flash memory reveals various error patterns by the devices it is mounted, and thus the memory makers are trying to minimize error ratio in the final process through not only the electric test but also the data integrity test under the same condition as real application devices. This process is called an application-level memory test. Though currently various flash memory testing devices have been used in the production lines, most of the works related to memory test depend on the sensual abilities of human testers. In case of testing the flash memory for MP3 devices, the human testers are checking if the memory has some errors by hearing the audio played on the memory testing device. The memory testing process like this has become a bottleneck in the flash memory production line. In this paper, we propose an audio comparison technique to support the efficient flash memory test for MP3 devices. The technique proposed in this paper compares the variance change rate between the source binary file and the decoded analog signal and checks automatically if the memory errors are occurred or not.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.5
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• pp.1013-1022
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• 2017

Windows hibernation is a function that stores data of physical memory on a non-volatile media and then restores the memory data from the non-volatile media to the physical memory when the system is powered on. Since the hibernation file has memory data in a static state, when the attacker collects it, key information in the system's physical memory may be leaked. Because Windows does not support protection for hibernation files only, we need to protect the memory that is written to the hibernate file. In this paper, we propose a method to encrypt the physical memory data in the hibernation file to protect the memory data of the processes recorded in the hibernation file. Hibernating procedure is analyzed to encrypt the memory data at the hibernating and the encryption process for hibernation memory is implemented to operate transparently for each process. Experimental results show that the hibernation process memory encryption tool showed about 2.7 times overhead due to the crypt cost. This overhead is necessary to prevent the attacker from exposing the plaintext memory data of the process.