• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• Structural Engineering and Mechanics
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• 제63권4호
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• pp.497-507
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• 2017

During recent earthquakes, a significant number of concrete structures suffered extensive damage. Conventional reinforced concrete structures are designed for life-time safety that may see permanent inelastic deformation after severe earthquakes. Hence, there is a need to utilize adequate materials that have the ability to tolerate large deformation and get back to their original shape. Super-elastic shape memory alloy (SMA) is a smart material with unique properties, such as the ability to regain undeformed shape by unloading or heating. In this research, four different stories (three, five, seven and nine) of reinforced concrete (RC) buildings have been studied and subjected to near-field ground motions. For each building, two different types of reinforcement detailing are considered, including (1) conventional steel reinforcement (RC frame) and (2) steel-SMA reinforcement (SMA RC frame), with SMA bars being used at plastic zones of beams and steel bars in other regions. Nonlinear time history analyses have been performed by "SeismoStruct" finite element software. The results indicate that the application of SMA materials in plastic hinge regions of the beams lead to reduction of the residual displacement and consequently post-earthquake repairs. In general, it can be said that shape memory alloy materials reduce structural damage and retrofit costs.

• 한국통신학회논문지
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• 제21권5호
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• pp.1325-1331
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• 1996

본 논문에서는 전류 스위칭(switched-current:SI) 시스템에서 THD(total harmonic distortion) 증가 원인인 클럭피드스루(clock feedthrough:CFT) 오차 전압을 감소시키는 새로운 전류 메모리(current-memory) 회로를 제안하였다. 제안한 전류 메모리는 CMOS 상보형의 PMOS 트랜지스터를 이용하여 CFT 오차 전압에 의한 출력 왜곡 전류를 감소시킨다. 제안한 전류 메모리 회로를 $1.2{\mu}{\textrm{m}}$ CMOS 공정을 사용하여 설계하고, 입력으로 전류 크기 $68{\mu}{\textrm{m}}$인 1MHz 정현파 신호를 인가하였다.(샘플링 주파수:20MHz) 모의 실험 결과, 기존의 전류 메모리보다 CFT 오차 전압에 의한 출력 왜곡 전류가 10배 정도 감소를 나타내었으며 신호 대 바이어스 전류비가 0.5(peak signal-to-bias current ratio:i/J)인 1KHz 신호를 인가할 경우 THD는 -57dB이다.

• Biomolecules & Therapeutics
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• 제22권3호
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• pp.232-238
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• 2014

Alzheimer's disease (AD) is the most common neurodegenerative disease without known ways to cure. A key neuropathologic manifestation of the disease is extracellular deposition of beta-amyloid peptide (Ab). Specific mechanisms underlying the development of the disease have not yet been fully understood. In this study, we investigated effects of 4-O-methylhonokiol on memory dysfunction in APP/PS1 double transgenic mice. 4-O-methylhonokiol (1 mg/kg for 3 month) significantly reduced deficit in learning and memory of the transgenic mice, as determined by the Morris water maze test and step-through passive avoidance test. Our biochemical analysis suggested that 4-O-methylhonokiol ameliorated $A{\beta}$ accumulation in the cortex and hippocampus via reduction in beta-site APP-cleaving enzyme 1 expression. In addition, 4-O-methylhonokiol attenuated lipid peroxidation and elevated glutathione peroxidase activity in the double transgenic mice brains. Thus, suppressive effects of 4-O-methylhonokiol on $A{\beta}$ generation and oxidative stress in the brains of transgenic mice may be responsible for the enhancement in cognitive function. These results suggest that the natural compound has potential to intervene memory deficit and progressive neurodegeneration in AD patients.

• 한국전기전자재료학회논문지
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• 제20권12호
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

• 한국통신학회논문지
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• 제24권12B호
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• pp.2424-2429
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• 1999

본 논문은 길쌈 부호화 (convolutional encoding) 및 인터리빙(interleaving) 기법을 사용하는 채널 부호기에 있어서 메모리 크기를 최소화한 설계 방법에 관한 것이다. 기존의 구현방식에서는 프레임 데이터를 보관하는 입력버퍼 RAM과 인터리빙을 위한 인터리버 RAM을 별도로 사용해야 한다. 본 논문에서는 메모리 크기가 큰 인터리버 RAM을 사용하는 대신 입력버퍼 RAM 1개를 추가로 사용하여 길쌈 부호화 및 인터리빙을 동시에 처리할 수 있는 새로운 채널 부호기 설계 방법을 제안하였다. 이 설계 방법을 여러 디지털 이동통신 모뎀의 채널 부호기에 적용한 결과 기존 설계 방식에 비해 33% ∼60%의 메모리 크기 감소 효과가 있었으며, 프레임 데이터 수신 시 처리 절차가 간편해지고 타이밍 마진을 늘일 수 있는 장점이 있었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 춘계학술대회
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• pp.486-489
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• 2010

IEEE 802.11n WLAN 표준의 블록길이 1,944비트, 부호화율 1/2을 지원하는 layered LDPC 복호기 프로세서를 설계하였다. 하드웨어 복잡도 감소를 위해 최소합 알고리듬과 layered 구조를 적용하였으며, 최소합 알고리듬의 특징을 이용하여 검사노드 메모리의 용량을 기존의 방법보다 75% 감소시켰다. 설계된 프로세서는 200,400 게이트와 19,400비트의 메모리로 구현되었으며, FPGA 구현을 통해 하드웨어 동작을 검증하였다. Xilinx사의 Virtex-4 FPGA XC4vlx25 디바이스로 합성한 결과 120 MHz 클록으로 동작하여 약 200 Mbps의 성능을 나타내었다.

• 대한음성학회지:말소리
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• 제52호
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• pp.111-120
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5 kbytes for program code. Maximum required time of 29.2 ms for processing a frame of 32 ms of speech validates real-time operation of the implemented system.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.384-384
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• 2012

We report nonvolatile memory properties of poly (3, 4-ethylenedioxythiophene) (PEDOT) thin films grown by vapor phase polymerization using FeCl3 as an oxidant. Liquid-bridge-mediated transfer method was employed to remove FeCl3 for generation of pure PEDOT thin films. From the electrical measurement of memory device, we observed voltage induced bipolar resistive switching behavior with ON/OFF ratio of 103 and reproducibility of more than 103 dc sweeping cycles. ON and OFF states were stable up to 104 seconds without significant degradation. Cyclic voltammetry data illustrates resistive switching effect can be attributed to formation and rupture of conducting paths due to oxidation and reduction of PEDOT. The maximum current before reset process was found to be increase linearly with increase in compliance current applied during set process.

• 대한전자공학회논문지
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• 제21권3호
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• pp.19-25
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• 1984

Microprogrammed 디지탈 시스템에서 재프로그램을 위한 가변성을 고려한 제어기억장치의 비트 폭을 최소화시키는 새로운 알고리즘을 제시한다. 본 알고리즘은 비트 폭을 최소화시킴과 동시에 weight가 높은 MOP에 고유영역을 부여함으로써 비트 최소화 과정시에 수반되는 가변성의 손실을 보상할 수 있다. 또 본 알고리즘을 프로그램하여 종래의 연구결과와 비교 검토하여 비트 감소와 가변성이 개선된 것을 중명하였다.