• The Korean Journal of Physiology and Pharmacology
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• v.1 no.2
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• pp.117-125
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• 1997

The N-methyl-D-aspartate (NMDA) receptor-mediated glutamatergic neurotransmission is involved in synaptic plasticity, developmental processes, learning and memory and many neuropathological disorders including age-related diseases. In the present study, regulation of the NMDA receptor properties by various ligands was investigated using $[^3H]MK-801$ binding studies in the synaptic membranes of young and aged rat forebrains. The binding in the presence of glutamate and glycine increased dramatically with growth between 1 and 6 weeks old, and thereafter declined gradually with aging. Glutamate, glycine or spermine respectively increased the binding with growth. Glutamate maintained the binding during aging, while glycine or spermine significantly decreased the binding in the aged brain. The maximum stimulation by glycine varied depending on the ages of brains. Greater sensitivity to glycine was observed at 1 week and 3 months and the sensitivity was significantly reduced in the aged brain. In contrast, spermine showed similar stimulation patterns in young and aged rats. These results indicated that the functional properties of the NMDA receptor-ion channel complex in young and aged rat forebrains are differentially regulated by agonists, and the reduction of the receptor function with normal aging may be, in some degree, due to the reduction of the receptor sensitivity to glycine.

• Journal of Korea Multimedia Society
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• v.20 no.11
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• pp.1750-1758
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• 2017

In super-resolution, various methods with Convolutional Neural Network(CNN) have recently been proposed. CNN based methods provide much higher image quality than conventional methods. Especially, VDSR outperforms other CNN based methods in terms of image quality. However, it requires a high computational complexity which prevents real-time processing. In this paper, the method to apply a deconvolution layer to VDSR is proposed to reduce computational complexity. Compared to original VDSR, the proposed method achieves the 4.46 times speed-up and its degradation in image quality is less than -0.1 dB which is negligible.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.44-46
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• 2005

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about $1Tb/cm^3$ can be realized. In this paper, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. We proposal Algorithm use The Extended Kalman filter. The Kalman filter reduce measurement noise. Therefore, By using this error reduction method following results are obtained; the effect of measurement nois of Pixel is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.129-133
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• 2005

Data storage related with writing and retrieving requires high storage capacity, fast transfer rate and less access time. Today any data storage system cannot satisfy these conditions, however holographic data storage system can perform faster data transfer rate because it is a page oriented memory system using volume hologram in writing and retrieving data. System can be constructed without mechanical actuating part therefore fast data transfer rate and high storage capacity about $1Tb/cm^3$ can be realized. In this paper, to reduce errors of binary data stored in holographic data storage system, a new method for bit error reduction is suggested. First, find cluster centers using subtractive clustering algorithm then reduce intensities of pixels around cluster centers and fuzzy rules. Therefore, By using this error reduction method following results are obtained ; the effect of Inter Pixel Interference noise is decreased and the intensity profile of data page becomes uniform therefore the better data storage system can be constructed.

• Journal of Information Processing Systems
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• v.4 no.4
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• pp.133-144
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• 2008

Clusters have become a popular alternative for building high-performance parallel computing systems. Today's high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDTbased NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes${\sim}$4 Kbytes) in a SAN environment.

• Smart Structures and Systems
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• v.25 no.3
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• pp.311-322
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• 2020

This paper studies the influence of parameters of a novel SMA helical spring energy dissipation brace on the seismic resistance of a frame structure. The force-displacement relationship of the SMA springs is established mathematically based on a multilinear constitutive model of the SMA material. Four SMA helical springs are fabricated, and the force-displacement relationship curves of the SMA springs are obtained via tension tests. A numerical dynamic model of a two-floor frame with spring energy dissipation braces is constructed and evaluated via vibration table tests. Then, two spring parameters, namely, the ratio of the helical spring diameter to the wire diameter and the pre-stretch length, are selected to investigate their influences on the seismic responses of the frame structure. The simulation results demonstrate that the optimal ratio of the helical spring diameter to the wire diameter can be found to minimize the absolute acceleration and the relative displacement of the frame structure. Meanwhile, if the pre-stretch length is assigned a suitable value, excellent vibration reduction performance can be realized. Compared with the frame structure without braces, the frames with spring braces exhibit highly satisfactory seismic resistance performance under various earthquake waves. However, it is necessary to select an SMA spring with optimal parameters for realizing optimal vibration reduction performance.

• Journal of Internet Computing and Services
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• v.22 no.3
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• pp.9-16
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• 2021

This study aims to develop a human activity recognition (HAR) system as a Deep-Learning (DL) classification model, distinguishing various human activities. We solely rely on the signals from a wristband accelerometer worn by a person for the user's convenience. 3-axis sequential acceleration signal data are gathered within a predefined time-window-slice, and they are used as input to the classification system. We are particularly interested in developing a Deep-Learning model that can outperform conventional machine learning classification performance. A total of 13 activities based on the laboratory experiments' data are used for the initial performance comparison. We have improved classification performance using the Convolutional Neural Network (CNN) combined with an auto-encoder feature reduction and parameter tuning. With various publically available HAR datasets, we could also achieve significant improvement in HAR classification. Our CNN model is also compared against Recurrent-Neural-Network(RNN) with Long Short-Term Memory(LSTM) to demonstrate its superiority. Noticeably, our model could distinguish both general activities and near-identical activities such as sitting down on the chair and floor, with almost perfect classification accuracy.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.2
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• pp.13-20
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• 2009

Recently there is growing interest in LBS requiring real-time services and the spatial main memory DBMS for efficient Telematics services. In order to optimize existing disk-based spatial indexes of the spatial main memory DBMS in the main memory, spatial index structures have been proposed, which minimize failures in cache access by reducing the entry size. However, because the reduction of entry size requires compression based on the MBR of the parent node or the removal of redundant MBR, the cost of MBR reconstruction increases in index update and the efficiency of search is lowered in index search. Thus, to reduce the cost of MBR reconstruction, this paper proposed the RSMB (relative-sized MBR)compression technique, which applies the base point of compression differently in case of broad distribution and narrow distribution. In case of broad distribution, compression is made based on the left-bottom point of the extended MBR of the parent node, and in case of narrow distribution, the whole MBR is divided into cells of the same size and compression is made based on the left-bottom point of each cell. In addition, MBR was compressed using a relative coordinate and size to reduce the cost of search in index search. Lastly, we evaluated the performance of the proposed RSMBR compression technique using real data, and proved its superiority.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.47-57
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• 2008

Recently, energy-efficient NAND Flash memory of large volume is favored as next-generation storage for sensor nodes. So far, most sensor node file systems are based on NOR flash and few file systems are applicable to large NAND flash memory. Although it is required to develop new file systems taking account of the features of NAND flash memory, it is difficult to develop them mainly due to the limit of SRAM memory on sensor nodes. Sensor nodes support SRAM of $4{\sim}10$ KBytes only. In this paper, we designed and implemented a novel file system to support data-centric applications. To do this, we added EEPROM of 1 KBytes to store persistent file description data efficiently and devised a simple wear-leveling method. This reduces the number of page updates, resulting in reduction in energy use and increase in lifetime of sensor nodes.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.11-20
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• 1999

The data transfer width between the mocroprocessor and the memory comes to a critical part that limits system performance since the data transfer width has been as it was while the performance of a microprocessor is getting higher due to its continuous development in speed. And it is important that the memory should be in small size for the reduction of embedded microprocessor's price which is integrated on a single chip with the memory and IO circuit. In this paper, a mocroprocessor tentatively named as Extendable Instruction Set Computer(EISC) is proposed as the high code density 32 bit mocroprocessor architecture. The 32 bit EISC has 16 general purpose registers and 16 bit fixed length instruction which has the short length offset and small immediate operand. By using and extend register and extend flag, the offset and immediate operand could be extended. The proposed 32 bit EISC is implemented with an FPGA and all of its functions have been tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit EISC shows 140-220% and 120-140% higher code density than RISC and CISC respectively, which is much higher than any other traditional architectures. As a consequence, the EISC is suitable for the next generation computer architecture since it requires less data transfer width compared to any other ones. And its lower memory requirement will embedded microprocessor more useful.