• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.10
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• pp.5035-5048
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• 2016

Nano scale networks are futuristic networks deemed as enablers for the Internet of Nano Things, Body area nano networks, target tracking, anomaly/ abnormality detection at molecular level and neuronal therapy / drug delivery applications. Molecular communication is considered the most compatible communication technology for nano devices. However, connectivity in such networks is very low due to inter-symbol interference (ISI). Few research papers have addressed the issue of ISI mitigation in molecular communication. However, many of these methods are not adaptive to dynamic environmental conditions. This paper presents an enhancement over original Memory-1 ISI cancellation scheme using maximum likelihood estimation of a channel parameter (λ) to make it adaptable to variable channel conditions. Results of the Monte Carlo simulation show that, the connectivity (P_conn) improves by 28% for given simulation parameters and environmental conditions by using enhanced Memory-1 cancellation method. Moreover, this ISI mitigation method allows reduction in symbol time (Ts) up to 50 seconds i.e. an improvement of 75% is achieved.

• Educational Technology International
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• v.10 no.2
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• pp.145-166
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• 2009

The purpose of this study was to investigate why advance organizers (AO) are effective in promoting comprehension and mental model formation in terms of cognitive load. Two experimental groups: a concept-map AO group and a key-word AO group and one control group were used. This study considered cognitive load in view of Baddeley's working memory model: central executive (CE), phonological loop (PL), and visuo-spatial sketch pad (VSSP). The present experiment directly examined cognitive load using dual task methodology. The results were as follows: central executive (CE) suppression task achievement for the concept map AO group was higher than the key word AO group and control group. Comprehension and mental model construction for the concept map AO group were higher than the other groups. These results indicated that the superiority of concept map AO owing to CE load decrement occurred with comprehension and mental model construction in learning. Thus, the available resources produced by CE load reduction may have been invested for comprehension and mental model construction of learning contents.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.6A
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• pp.551-557
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• 2011

We investigate lattice-reduction-aided precoding techniques using Look-Up table (LUT) for multi-user multiple-input multiple-output(MIMO) systems. Lattice-reduction-aided vector perturbation (VP) gives large sum capacity with low encoding complexity. Nevertheless lattice-reduction process based on the LLL-Algorithm still requires high computational complexity since it involves several iterations of size reduction and column vector exchange. In this paper, we apply the LUT-aided lattice reduction on VP and propose a scheme to generate the LUT efficiently. Simulation results show that a proposed scheme has similar orthogonality defect and Bit-Error-Rate(BER) even with lower memory size.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.15 no.5
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• pp.125-133
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• 2016

Data processing capacity and speed are rapidly increasing due to the development of hardware and software in recent time. As a result, data usage is geometrically increasing and the amount of data which computers have to process has already exceeded five-thousand transaction per second. That is, the importance of Big Data is due to its 'real-time' and this makes it possible to analyze all the data in order to obtain accurate data at right time under any circumstances. Moreover, there are many researches about this as construction of smart factory with the application of Big Data is expected to have reduction in development, production, and quality management cost. In this paper, system using In-Memory Data Grid for high speed processing is implemented in semiconductor process which numerous data occur and improved performance is proven with experiments. Implemented system is expected to be possible to apply on not only the semiconductor but also any fields using Big Data and further researches will be made for possible application on other fields.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.32-38
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• 2009

FTT(Fast Fourier Transform) processor is widely used in OFDM(Orthogonal Frequency Division Multiplesing) system. Because of the increased requirement of mobility and bandwidth in the OFDM system, they need large point FTT processor. Since the size of memory which stores the twiddle factor coefficients are proportional to the N of FFT size, we propose a new method by which we can reduce the size of the coefficient memory. In the proposed method, we exploit a counter and unsigned multiplier to generate the twiddle factor indices. To verify the proposed algorithm, we design TFCGs(Twiddle Factor Coefficient Generator) for 1024pint FFTs with R2SDF(Radix-2 Single-Path Delay Feedback), $R2^3SDF,\;R2^3SDF,\;R2^4SDF$ architectures. The size of ROM is reduced to 1/8N. In the case of $R2^4SDF$ architecture, the area and the power are reduced by 57.9%, 57.5% respectively.

• Journal of KIISE:Databases
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• v.31 no.4
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• pp.384-394
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• 2004

Recently, to relieve the performance degradation caused by the bottleneck between CPU and main memory, cache conscious multi-dimensional index structures have been proposed. The ultimate goal of them is to reduce the space for entries so as to widen index trees and minimize the number of cache misses. The existing index structures can be classified into two approaches according to their entry reduction methods. One approach is to compress MBR keys by quantizing coordinate values to the fixed number of bits. The other approach is to store only the sides of minimum bounding regions (MBRs) that are different from their parents partially. In this paper, we propose a new index structure that exploits the properties of the both techniques. Then, we investigate the existing multi-dimensional index structures for main memory database system through experiments under the various work loads. We perform various experiments to show that our approach outperforms others.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.111-121
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• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.7
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• pp.349-358
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• 2005

False sharing is a result of co-location of unrelated data in the same unit of memory coherency, and is one source of unnecessary overhead being of no help to keep the memory coherency in multiprocessor systems. Moreover. the damage caused by false sharing becomes large in proportion to the granularity of memory coherency. To reduce false sharing in a page-based DSM system, it is necessary to allocate unrelated data objects that have different access patterns into the separate shared pages. In this paper we propose call-site tracing-based shared memory allocator. shortly CSTallocator. CSTallocator expects that the data objects requested from the different call-sites may have different access patterns in the future. So CSTailocator places each data object requested from the different call-sites into the separate shared pages, and consequently data objects that have the same call-site are likely to get together into the same shared pages. We use execution-driven simulation of real parallel applications to evaluate the effectiveness of our CSTallocator. Our observations show that by using CSTallocator a considerable amount of false sharing misses can be additionally reduced in comparison with the existing techniques.

• Journal of IKEEE
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• v.28 no.1
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• pp.110-115
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• 2024

This paper analyzed the V_th (Threshold Voltage) variations in 3D NAND Flash memory with tapered O/N/O (Oxide/Nitride/Oxide) structure and O/N/F (Oxide/Nitride/Ferroelectric) structure, where the blocking oxide is replaced by ferroelectric material. With a tapering angle of 0°, the O/N/F structure exhibits lower resistance compared to the O/N/O structure, resulting in reduced V_th variations in both the upper and lower regions of the WL (Word Line). Tapered 3D NAND Flash memory shows a decrease in channel area and an increase in channel resistance as it moves from the upper to the lower WL. Consequently, as the tapering angle increases, the V_th decreases in the upper WL and increases in the lower WL. The tapered O/N/F structure, influenced by V_fe proportional to the channel radius, leads to a greater reduction in V_th in the upper WL compared to the O/N/O structure. Additionally, the lower WL in the O/N/F structure experiences a greater increase in V_th compared to the O/N/O structure, resulting in larger V_th variations with increasing tapering angles.