• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• Structural Engineering and Mechanics
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• v.63 no.4
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• pp.497-507
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• 2017

During recent earthquakes, a significant number of concrete structures suffered extensive damage. Conventional reinforced concrete structures are designed for life-time safety that may see permanent inelastic deformation after severe earthquakes. Hence, there is a need to utilize adequate materials that have the ability to tolerate large deformation and get back to their original shape. Super-elastic shape memory alloy (SMA) is a smart material with unique properties, such as the ability to regain undeformed shape by unloading or heating. In this research, four different stories (three, five, seven and nine) of reinforced concrete (RC) buildings have been studied and subjected to near-field ground motions. For each building, two different types of reinforcement detailing are considered, including (1) conventional steel reinforcement (RC frame) and (2) steel-SMA reinforcement (SMA RC frame), with SMA bars being used at plastic zones of beams and steel bars in other regions. Nonlinear time history analyses have been performed by "SeismoStruct" finite element software. The results indicate that the application of SMA materials in plastic hinge regions of the beams lead to reduction of the residual displacement and consequently post-earthquake repairs. In general, it can be said that shape memory alloy materials reduce structural damage and retrofit costs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1325-1331
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• 1996

In this paper, a new current-memory circuit is proposed that reduces the clock feedthrough(CFT) error voltage causing total harmonic distortion(THD) increment in switched-current(SI) systems. Using PMOS transistor in CMOS complementary, the proposed one reduces output distortion current due to the CFT errorvoltage. A proposed current-memory is designed using a 1.2.mu.m CMOS process anda 1MHz sinusoidal signal having a 68.mu.A amplitude current is applied as input (sampling frequency:20MHz). It hasbeen shown from the simulation that the output distortion current effected by the CFT error voltage is reduced by approximately 10 times the error voltage of conventional one, THD is -57dB in case ofappling 1kHz frequency input signalwith 0.5 peak signal-to-bias current ratio.

• Biomolecules & Therapeutics
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• v.22 no.3
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• pp.232-238
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• 2014

Alzheimer's disease (AD) is the most common neurodegenerative disease without known ways to cure. A key neuropathologic manifestation of the disease is extracellular deposition of beta-amyloid peptide (Ab). Specific mechanisms underlying the development of the disease have not yet been fully understood. In this study, we investigated effects of 4-O-methylhonokiol on memory dysfunction in APP/PS1 double transgenic mice. 4-O-methylhonokiol (1 mg/kg for 3 month) significantly reduced deficit in learning and memory of the transgenic mice, as determined by the Morris water maze test and step-through passive avoidance test. Our biochemical analysis suggested that 4-O-methylhonokiol ameliorated $A{\beta}$ accumulation in the cortex and hippocampus via reduction in beta-site APP-cleaving enzyme 1 expression. In addition, 4-O-methylhonokiol attenuated lipid peroxidation and elevated glutathione peroxidase activity in the double transgenic mice brains. Thus, suppressive effects of 4-O-methylhonokiol on $A{\beta}$ generation and oxidative stress in the brains of transgenic mice may be responsible for the enhancement in cognitive function. These results suggest that the natural compound has potential to intervene memory deficit and progressive neurodegeneration in AD patients.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12B
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• pp.2424-2429
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• 1999

In this paper, we present a memory efficient implementation method of channel encoder using convolutional encoding and interleaving. In conventional method, two separate RAMs must be used for the channel encoder: one RAM for storing frame data and another RAM for interleaving. In our method, without using interleaving RAM, we only use two small RAMs for buffering input frame data. We can process convolutional encoding and interleaving concurrently by using the two RAMs. There are several advantages when applying channel encoder designed using this method to several digital mobile telecommunications : the reduction of memory size ranging 33 % - 60 %, simplified procedure of receiving frame data, and resultant timing margin gained by the simplified procedure.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.486-489
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• 2010

This paper describes a layered LDPC decoder which supports block length of 1,944 bits and code rate 1/2 for IEEE 802.11n WLAN standard. To reduce the hardware complexity, the min-sum algorithm and layered architecture is adopted. A novel memory reduction technique suitable for min-sum algorithm reduces memory size by 75% compared with conventional method. The designed processor has 200,400 gates and 19,400 bits memory, and it is verified by FPGA implementation. The estimated throughput is about 200 Mbps at 120 MHz clock by using Xilinx Virtex-4 FPGA device.

• MALSORI
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• no.52
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• pp.111-120
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• 2004

This paper focuses on the DSP implementation of an HMM-based speech recognizer that can handle several hundred words of vocabulary size as well as speaker independency. First, we develop an HMM-based speech recognition system on the PC that operates on the frame basis with parallel processing of feature extraction and Viterbi decoding to make the processing delay as small as possible. Many techniques such as linear discriminant analysis, state-based Gaussian selection, and phonetic tied mixture model are employed for reduction of computational burden and memory size. The system is then properly optimized and compiled on the TMS320C6711 DSP for real-time operation. The implemented system uses 486kbytes of memory for data and acoustic models, and 24.5 kbytes for program code. Maximum required time of 29.2 ms for processing a frame of 32 ms of speech validates real-time operation of the implemented system.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.384-384
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• 2012

We report nonvolatile memory properties of poly (3, 4-ethylenedioxythiophene) (PEDOT) thin films grown by vapor phase polymerization using FeCl3 as an oxidant. Liquid-bridge-mediated transfer method was employed to remove FeCl3 for generation of pure PEDOT thin films. From the electrical measurement of memory device, we observed voltage induced bipolar resistive switching behavior with ON/OFF ratio of 103 and reproducibility of more than 103 dc sweeping cycles. ON and OFF states were stable up to 104 seconds without significant degradation. Cyclic voltammetry data illustrates resistive switching effect can be attributed to formation and rupture of conducting paths due to oxidation and reduction of PEDOT. The maximum current before reset process was found to be increase linearly with increase in compliance current applied during set process.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.3
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• pp.19-25
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• 1984

This paper suggests a new algorithm which minimizes the bit dimension of control memory considering the flexibility for reprogramming in the microprogrammed digital systems. The algorithm can not only minimize the bit dimension but also compensate the loss of flexibility by giving a highest MOP the unique field in the process of bit minimization. Also, programming the algorithm, that result and previous works are compared and reviewed. Then the bit reduction and the improvement of flexibility are proved.