• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제15권12호
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• pp.958-962
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• 2009

최근 저장장치로 하드 디스크를 대치하고 있는 플래시 메모리 저장장치는 물리적 특성이 하드디스크와 다르다. 이러한 플래시 메모리 저장장치의 성능을 향상시키기 위해 운영체제 및 파일시스템의 여러 계층에 걸쳐 다양한 연구가 진행되고 있다. 본 연구에서는 파일 삭제시 무효화되는 페이지 정보를 상위 계층에서 전달받아 이를 저장하고 활용하는 플래시 메모리 저장장치의 구조를 제안하고 해당 시스템의 성능 및 영향에 대해 연구하였다. 제안하는 시스템은 페이지 무효 정보를 블록 병합, 웨어 레벨링 등에 활용하고 이에 따라 시스템의 성능을 효과적으로 향상시키는 것으로 나타났다.

• 디지털산업정보학회논문지
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• 제11권4호
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• pp.1-12
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• 2015

This research analyzes the current state of the semiconductor industry delivering the prediction for the future development of the semiconductor industry along with some semiconductor memory's responsive strategies. In the 2014, top 10 semiconductor companies were targeted and studied its growth based on its profitability and growth indications in perspective during three years. The system semiconductor industry with the increase in Hyper-scale customers, proactive actions in the technology consortium, is polarizing caused by increased R&D expense to ensure process scaling limits and high performance, and some results have shown: PC and Mobile slowdown and growth recession phenomenon due to IoT's unclear direction. The leading company is to secure new growth engines through 'Acquiring'. While as the subordinated companies following this consecutive survival through the 'Acquired', the future of system semiconductor industry is to strengthen the market dominance and its techniques by concentrating on the reorganization of the market by few large companies. Accordingly, the semiconductor memory industry is expected to reach the limit of its expansion to domain of system semiconductor, and it is highly suggesting the need of the 'Memory Life Extension' growth strategy.

• Journal of Information Processing Systems
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• 제17권1호
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• pp.191-202
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• 2021

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program's computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

• 정보과학회 컴퓨팅의 실제 논문지
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• 제23권7호
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• pp.428-433
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• 2017

최근 데이터센터, 소셜 네트워크 서비스 등과 같은 고성능 컴퓨팅을 요구하는 환경에서는 기존 하드디스크를 대체할 수 있는 고성능 비휘발성 메모리 저장장치의 수요가 급증하고 있다. 이러한 비휘발성 메모리의 성능은 호스트와 저장장치를 연결해주는 인터페이스에 따라 크게 좌우될 수 있다. 저장장치의 인터페이스는 계속 발전해왔으며, 기존 하드디스크에 기반을 둔 SAS/SATA 인터페이스를 대체할 수 있는 NVMe 인터페이스가 최근에 등장하였다. NVMe 인터페이스는 높은 확장성을 가지며 기존 인터페이스에 비해 낮은 지연시간을 제공한다. 본 논문은 다양한 워크로드를 통해 NVMe 저장장치의 성능을 평가하고 분석한다. 또한 NVMe 저장장치와 기존 SATA 저장장치와의 가격 대비 성능비를 비교하고 평가한다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1986년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 17-18 Oct. 1986
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• pp.97-101
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• 1986

This paper deals with the problem of stability and error analyses of the FIR filter and the limited memory filters. It is shown that the FIR filter has the best performance among them, which is demonstrated by some simple examples and via simulations.

• 대한임베디드공학회논문지
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• 제13권5호
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• pp.261-268
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• 2018

Phase Change Memory(PCM) with low power consumption and high integration attracts attention as a next generation nonvolatile memory replacing DRAM. However, there is a problem that PCM has long latency and high energy consumption due to the writing operation. The PCM & DRAM hybrid memory structure is a fruitful structure that can overcome the disadvantages of such PCM. However, the page replacement algorithm is important, because these structures use two memory of different characteristics. The purpose of this document is to effectively manage pages that can be referenced in memory, taking into account the characteristics of DRAM and PCM. In order to manage these pages, this paper proposes an page replacement algorithm based on frequently accessed and recently paged. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the energy-delay product by around 10%, compared with Clock-DWF and CLOCK-HM.

• 대한임베디드공학회논문지
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• 제11권2호
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• pp.57-65
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• 2016

In this paper, we propose a system for efficient use of shared memory between CPU and GPU. The system, called Fusion Architecture, assures consistency of the shared memory and minimizes cache misses that frequently occurs on Heterogeneous System Architecture or Unified Virtual Memory based systems. It also maximizes the performance for memory intensive jobs by efficient allocation of GPU cores. To test between architectures on various scenarios, we introduce the Fusion Architecture Analyzer, which compares OpenMP, OpenCL, CUDA, and the proposed architecture in terms of memory overhead and process time. As a result, Proposed fusion architectures show that the Fusion Architecture runs benchmarks 55% faster and reduces memory overheads by 220% in average.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• 한국멀티미디어학회논문지
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• 제24권7호
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• pp.922-932
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• 2021

This thesis mainly studies the impact of short-term memory in VR tour games on users. The thesis is based on VR tour games and short-term memory, using the literature research method, the practical research method, and the investigation method. First, the author designs and makes VR tour games on the Beijing-Hangzhou Grand Canal, and then conducts a questionnaire survey and designs a control experiment. The experiment explores the differences of the short-term memory level of individuals between the normal environment and the VR tour game environment. It verifies whether the influential hypothesis proposed by the research is correct. Research conclusions show that: VR tour games have an impact on short-term memory. Compared with the normal environment, the subjects have better performance in the VR tour game mode and can maintain a high short-term memory level for a longer time. Its conclusions should promote the cultural propaganda of scenic spots and provide theoretical support for tourists' short-term memory of scenic spots culture.

• 한국정보과학회논문지:시스템및이론
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• 제31권1_2호
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• pp.125-134
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• 2004

최근에 프로세서-메모리간 성능격차 문제를 완화하기 위하여 내장캐시의 접근실패율을 낮추고 메모리 대역폭을 확장하는 내장캐시 압축시스템이 제안되었다. 내장캐시 압축시스템은 데이타를 압축해 저장함으로써 내장캐시의 실질적 저장공간을 확장하고, 메모리 버스에서 데이타를 압축해 전송함으로써 실질적 메모리 대역폭을 확장한다. 본 논문에서는 이와 같은 내장캐시 압축시스템을 확장해 기존의 주 메모리 압축시스템과 병합해 설계한 이종 메모리 압축시스템을 제안한다. 주 메모리의 기억공간을 효율적으로 확장하고, 내장캐시의 접근실패율을 낮추고, 메모리 대역폭을 확장하고, 압축캐시의 복원시간을 줄이고, 설계 복잡도를 낮추기 위하여 몇 가지 새로운 기법들을 제시한다. 제안하는 시스템과 비교대상 시스템의 성능은 슈퍼스칼라 구조의 마이크로프로세서 시뮬레이터를 수정하여 실행기반 시뮬레이션을 통해 검증한다. 본 논문에서 사용한 실험방법은 기존의 트레이스기반 시뮬레이션과 비교해 보다 높은 정확도를 갖는다. 실험결과 주 메모리 확장에 따른 이득을 고려하지 않은 경우에 제안하는 시스템은 일반 메모리시스템에 비하여 수행시간을 내장캐시의 크기에 따라 최대 4-23%가량 단축한다. 제안하는 시스템의 데이타 메모리와 코드 메모리의 확장비율은 각각 57-120%와 27-36%이다.