• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.19-28
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• 2009

Computer system performance has always had the possibility of affecting business profitability, but with the advent of the World Wide Web where customers interact directly with Web servers, response time can have a direct and dramatic impact on business revenue. This paper is written in the operation environment and system analysis of HTS(Home Trading System) running K Securities. This paper also shows the method for performance improvement through investigation and analysis for the overall systems resources whether HTS has an appropriate performance or not. Performance analysis includes specially CPU analysis, Memory analysis, Disk Input/Output analysis and application analysis. Besides providing more detailed server specification for expansion from now on, system performance can be maintained with effect in the future. Through this study it is possible to manage the performance of HTS more easily and to solve problems such as a bottleneck more quickly.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.325-328
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. In this paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced $\Delta$ Rp increase using buffered N- implantation with tilt and 4X-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N- concentration which is intentionally caused by Ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.10
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• pp.94-101
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• 2004

This paper presents the development of a keypad test system for the improvement of working environment and productivity using PTC 16F877 microprocessor. In order to detect the fault of keypad products, hardware and software design is performed in this system. Keypad fault detection system is controlled by the 8 bit one chip PIC microcontroller for the exactness and speed. Developed panel of the keypad test system is comprised of the sub-panel for selecting in the inspected keypad types and the main panel f3r displaying the working order and fault position. Furthermore, all data from keypad inspection are stored in main memory of personal computer for the database. All these functions lead to the improvement of working speed and environment.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.6
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• pp.289-297
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• 2020

Although flash disks are being used widely instead of hard disks, it is difficult to optimize for effective utilization of flash disks because overwrite in place is impossible and the power consumption and time required for read, write, and erase operations are all different. One of these optimization issues is a cache management strategy to minimize write operations. The cache operates at two levels: an operating system equipped with flash disks and a translation layer within the flash disk. Most studies deal with the operating system-level cache strategy. In this study, we implement and analyse the DPW-LRU algorithm which is one of the recently proposed operating system cache replacement algorithms to apply to FTL, and grope with some improvements. As a result of the experiment, the DPW-LRU algorithm maintained superiority even in the FTL environment, and showed better performance with a slight improvement.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.68-75
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• 2009

As the recent performance of microprocessor is improving quickly, the necessity of cache is growing because of the increase of the access time of main memory. Every block of direct-mapped cache maps to one cache line. Although the mapping rule is simple, if different blocks map to one cache line, the miss ratio will be higher than the set-associative cache due to conflicts. In this paper, for the improvement of the direct-mapped cache of OpenRISC, 4-way set-associative cache is proposed. Four blocks of the main memory of the proposed cache map to one cache line so that the miss ratio is less than the direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The OpenRISC core including the 4-way set-associative cache was verified with FPGA emulation. As the result of performance measurement using test program, the performance of the OpenRISC core including the 4-way set-associative cache is higher than the previous one by 50% and the decrease of miss ratio is more than 15%.

• Korean Journal of Optics and Photonics
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• v.15 no.1
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• pp.79-85
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• 2004

We report on a transmittance controlled photomask with phase patterns on the back quartz surface. Theoretical analysis for changes in illumination pupil shape with respect to the variation of size and density of backside phase patterns and experimental results for improvement of critical dimension uniformity on a wafer by using the transmittance controlled photomask are presented. As phase patterns for controlling transmittance of the photomask we used etched contact-hole type patterns with 180" rotative phase with respect to the unetched region. It is shown that pattern size on the backside of the photomask must be made as small as possible in order to keep the illumination pupil shape as close as possible to the original pupil shape and to achieve as large an illumination intensity drop as possible at a same pattern density. The distribution of illumination intensity drop suitable for correcting critical dimension error was realized by controlling pattern density of the contact-hole type phase patterns. We applied this transmittance controlled photomask to a critical layer of DRAM (Dynamic Random Access Memory) having a 140nm design rule and could achieve improvement of the critical dimension uniformity value from 24.0 nm to 10.7 nm in 3$\sigma$.TEX>.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.1
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• pp.23-28
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• 2012

The performance improvement of the secondary storage is very slow compared to the main memory and processor. The data is loaded from secondary storage to memory for the execution of an application. At this time, there is a bottleneck. In this paper, we propose an Executable Compression Method to speed up the initial loading time of application. and we examined the performance. So we implemented the two applications. The one is a compressor for Execution Binary File. and The other is a decoder of Executable Compressed application file on the Embedded System. Using the test binary files, we performed the speed test in the six files. At the result, one result showed that the performance was decreased. but others had a increased performance. the average increasing rate was almost 29% at the initial loading time. The level of compression had different characteristics of the file. And the performance level was dependent on the file compressed size and uncompress time. so the optimized compression algorithm will be needed to apply the execution binary file.

• Nutrition Research and Practice
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• v.10 no.3
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• pp.274-281
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• 2016

BACKGROUND/OBJECTIVES: The accumulation of amyloid-${\beta}$ ($A{\beta}$) in the brain is a hallmark of Alzheimer's disease (AD) and plays a key role in cognitive dysfunction. Perilla frutescens var. japonica extract (PFE) and its major compound, rosmarinic acid (RA), have shown antioxidant and anti-inflammatory activities. We investigated whether administration of PFE and RA contributes to cognitive improvement in an $A{\beta}_{25-35}$-injected mouse model. MATERIALS/METHODS: Male ICR mice were intracerebroventricularly injected with aggregated $A{\beta}_{25-35}$ to induce AD. $A{\beta}_{25-35}$-injected mice were fed PFE (50 mg/kg/day) or RA (0.25 mg/kg/day) for 14 days and examined for learning and memory ability through the T-maze, object recognition, and Morris water maze test. RESULTS: Our present study demonstrated that PFE and RA administration significantly enhanced cognition function and object discrimination, which were impaired by $A{\beta}_{25-35}$, in the T-maze and object recognition tests, respectively. In addition, oral administration of PFE and RA decreased the time to reach the platform and increased the number of crossings over the removed platform when compared with the $A{\beta}_{25-35}$-induced control group in the Morris water maze test. Furthermore, PFE and RA significantly decreased the levels of nitric oxide (NO) and malondialdehyde (MDA) in the brain, kidney, and liver. In particular, PFE markedly attenuated oxidative stress by inhibiting production of NO and MDA in the $A{\beta}_{25-35}$-injected mouse brain. CONCLUSIONS: These results suggest that PFE and its active compound RA have beneficial effects on cognitive improvement and may help prevent AD induced by $A{\beta}$.

• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.141-149
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• 2006

In this paper, we introduce an improved algorithm for computing matrix triple product that commonly arises in primal-dual optimization method. In computing $P=AHA^{t}$, we devise a single pass algorithm that exploits the block diagonal structure of the matrix H. This one-phase scheme requires fewer floating point operations and roughly half the memory of the generic two-phase algorithm, where the product is computed in two steps, computing first $Q=HA^{t}$ and then P=AQ. The one-phase scheme achieved speed-up of 2.04 on Intel Itanium II platform over the two-phase scheme. Based on memory latency and modeled cache miss rates, the performance improvement was evaluated through performance modeling. Our research has impact on performance tuning study of complex sparse matrix operations, while most of the previous work focused on performance tuning of basic operations.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.1
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• pp.9-16
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• 2020

Recently, the capacity of SSD has been increasing rapidly due to the improvement of flash memory density. To take full advantage of these SSDs, first of all, FTL's prompt adaptation is necessary. The FTL is a translation layer existing in SSDs to overcome the drawback of the SSD that cannot be modified in place, and has garbage collection and caching functions in addition to the map table management function. In this study, we focus on caching function, compare and analyze the cache implementation methodologies, and propose improved methods. Typical cache implementations divide the cache into groups, manage and retrieve the caches in the group as a linked list. Thus, searches are made in the order of the linked list. In contrast, we propose a method of sequential searching using the search area group of a cache registered in the map table regardless of the linked list and cache group. Experimental results show that the proposed method has a 2.5 times improvement over the conventional method.