• Title/Summary/Keyword: Memory improvement

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Modified TDS (Task Duplicated based Scheduling) Scheme Optimizing Task Execution Time (태스크 실행 시간을 최적화한 개선된 태스크 중복 스케줄 기법)

  • Jang, Sei-Ie;Kim, Sung-Chun
    • Journal of KIISE:Computer Systems and Theory
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    • v.27 no.6
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    • pp.549-557
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    • 2000
  • Distributed Memory Machine(DMM) is necessary for the effective computation of the data which is complicated and very large. Task scheduling is a method that reduces the communication time among tasks to reduce the total execution time of application program and is very important for the improvement of DMM. Task Duplicated based Scheduling(TDS) method improves execution time by reducing communication time of tasks. It uses clustering method which schedules tasks of the large communication time on the same processor. But there is a problem that cannot optimize communication time between task sending data and task receiving data. Hence, this paper proposes a new method which solves the above problem in TDS. Modified Task Duplicated based Scheduling(MTDS) method which can approximately optimize the communication time between task sending data and task receiving data by checking the optimal condition, resulted in the minimization of task execution time by reducing the communication time among tasks. Also system modeling shows that task execution time of MTDS is about 70% faster than that of TDS in the best case and the same as the result of TDS in the worst case. It proves that MTDS method is better than TDS method.

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Design 5Q MPI Hardware Unit Supporting Standard Mode (표준 모드를 지원하는 5Q MPI 하드웨어 유닛 설계)

  • Park, Jae-Won;Chung, Won-Young;Lee, Seung-Woo;Lee, Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.1B
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    • pp.59-66
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    • 2012
  • The use of MPSoC has been increasing because of a rise of use of mobile devices and complex applications. For improving the performance of MPSoC, number of processor has been increasing. Standard MPI is used for efficiently sending data in distributed memory architecture that has advantage in multi processor. Standard In this paper, we propose a scalable distributed memory system with a low cost hardware message passing interface(MPI). The proposed architecture improves transfer rate with buffered send for small size packet. Three queues, Ready Queue, Request Queue, and Reservation Queue, work as previous architecture, and two queues, Small Ready Queue and Small Request Queue, are added to send small size packet. When the critical point is set 8 bytes, the proposed architecture takes more than 2 times the performance improvement in the data that below the critical point.

Progress of High-k Dielectrics Applicable to SONOS-Type Nonvolatile Semiconductor Memories

  • Tang, Zhenjie;Liu, Zhiguo;Zhu, Xinhua
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.4
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    • pp.155-165
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    • 2010
  • As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

A DOUBLE-BLIND CLINICAL TRIAL OF PANAX GINSENG IN AGED SUBJECTS (이중 맹검법을 이용한 홍삼의 노인병 치료에 대한 임상연구)

  • Fulder Stephen;Kataria Mohan;Smith Beryl Gethyn
    • Proceedings of the Ginseng society Conference
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    • 1984.09a
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    • pp.215-223
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    • 1984
  • Panax ginseng has often been suggested as a geriatric restorative. This study is a double blind crossover trial to test whether ginseng can improve function in subjects with the depression and reduced abilities associated with senescence. 49 screened subjects were given 1500 mg Korean Red ginseng and identical placebo each for ten days, with a washout period in between the dosages. Standard tests of mental function, neuromuscular reflexes, responsiveness, mood and well being were used. The subjects were somewhat better at the co-ordination and speed test ('number copying') but tests of concentration and memory ('Concentration', 'Paired Association', 'Digit Span' and 'Object Learning') gave equivocal results. There were small improvements in mood and well being ('Life Satisfaction' and 'General Health Questionnaire') while the subjects indicated increased energy, alertness and less sleep, but also less happiness on the daily analogue scales. The major result was a highly significant improvement in reactivity, speed and co-oridnation at the tapping test, and the visual, auditory and disjunctive reaction timer. These are the most objective and accurate tests used in this trial. It is therefore concluded that ginseng can increase function in senile individuals. This effect is most easily visualisable in objective psychophysical tests, rather than the more subjective memory and concentration tests.

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Functional Improvement of the Compressed Data Management System for Mobile DBMS (모바일 DBMS를 위한 압축 데이터 관리 시스템의 기능 고도화)

  • Hwang, Jin-Ho;Lee, Jeong-Wha;Kim, Gun-Woo;Shin, Young-Jae;Son, Jin-Hyun
    • The KIPS Transactions:PartD
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    • v.15D no.6
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    • pp.733-740
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    • 2008
  • Recently, mobile computing devices are used popularly. And quantity of information on mobile computing devices is being increased due to digitalization of information. So it needs an embedded DBMS for effective information management. Furthermore, since flash memory having a restriction on the number of partial write cycles is rapidly deployed on mobile computing devices as data storage and is more expensive than the conventional magnetic hard disk, the compressed data management system(CDMS) has been considered as an effective storage management technique for mobile computing devices in previous research. However, the research of CDMS is at the initial stage and has several problems. Hence, in this paper, we present additional storage management methods to solve the problems and improve the effectiveness of the CDMS for embedded DBMS.

Design of an Efficient VLSI Architecture of SADCT Based on Systolic Array (시스톨릭 어레이에 기반한 SADCT의 효율적 VLSl 구조설계)

  • Gang, Tae-Jun;Jeong, Ui-Yun;Gwon, Sun-Gyu;Ha, Yeong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.3
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    • pp.282-291
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    • 2001
  • In this paper, an efficient VLSI architecture of Shape Adaptive Discrete Cosine Transform(SADCT) based on systolic array is proposed. Since transform size in SADCT is varied according to the shape of object in each block, it are dropped that both usability of processing elements(PE´s) and throughput rate in time-recursive SADCT structure. To overcome these disadvantages, it is proposed that the architecture based on a systolic way structure which doesn´t need memory. In the proposed architecture, throughput rate is improved by consecutive processing of one-dimensional SADCT without memory and PE´s in the first column are connected to that in the last one for improvement of usability of PE. And input data are put into each column of PE in parallel according to the maximum data number in each rearranged block. The proposed architecture is described by VHDL. Also, its function is evaluated by MentorTM. Even though the hardware complexity is somewhat increased, the throughput rate is improved about twofold.

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Janus-FTL Adjusting the Size of Page and Block Mapping Areas using Reference Pattern (참조 패턴에 따라 페이지 및 블록 사상 영역의 크기를 조절하는 Janus-FTL)

  • Kwon, Hun-Ki;Kim, Eun-Sam;Choi, Jong-Moo;Lee, Dong-Hee;Noh, Sam-H.
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.12
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    • pp.918-922
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    • 2009
  • Naturally, block mapping FTL works well for sequential writes while page mapping FTL does well for random writes. To exploit their advantages, a practical FTL should be able to selectively apply a suitable scheme between page and block mappings for each write pattern. To meet that requirement, we propose a hybrid mapping FTL, which we call Janus-FTL, that distributes data to either block or page mapping areas. Also, we propose the fusion operation to relocate the data from block mapping area to page mapping area and the defusion operation to relocate the data from page mapping area to block mapping area. And experimental results of Janus-FTL show performance improvement of maximum 50% than other hybrid mapping FTLs.

Search Performance Improvement of Column-oriented Flash Storages using Segmented Compression Index (분할된 압축 인덱스를 이용한 컬럼-지향 플래시 스토리지의 검색 성능 개선)

  • Byun, Siwoo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.14 no.1
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    • pp.393-401
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    • 2013
  • Most traditional databases exploit record-oriented storage model where the attributes of a record are placed contiguously in hard disk to achieve high performance writes. However, for search-mostly datawarehouse systems, column-oriented storage has become a proper model because of its superior read performance. Today, flash memory is largely recognized as the preferred storage media for high-speed database systems. In this paper, we introduce fast column-oriented database model and then propose a new column-aware index management scheme for the high-speed column-oriented datawarehouse system. Our index management scheme which is based on enhanced $B^+$-Tree achieves high search performance by embedded flash index and unused space compression in internal and leaf nodes. Based on the results of the performance evaluation, we conclude that our index management scheme outperforms the traditional scheme in the respect of the search throughput and response time.

The Image Summarization Algorithm for Reviewing the Virtual Reality Experience (가상현실 경험을 복습시켜주는 사진 정리 알고리즘)

  • Kwak, Eun-Joo;Cho, Yong-Joo;Cho, Hyun-Sang;Park, Kyoung-Shin
    • The KIPS Transactions:PartB
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    • v.15B no.3
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    • pp.211-218
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    • 2008
  • In this paper, we proposed a new image summarization algorithm designed for automatically summarizing user's snapshot photos taken in a virtual environment based on user's context information and educational contents, and then presenting a summarized photos shortly after user's virtual reality experience. While other image summarization algorithms used date, location, and keyword to effectively summarize a large amount of photos, this algorithm is intended to improve users' memory retention by recalling their interests and important educational contents. This paper first describes some criteria of extracting the meaningful images to improve learning effects and the identification rate calculations, followed by the system architecture that integrates the virtual environment and the viewer interface. It will also discuss a user study to model the algorithm's optimal identification rate and then future research directions.

Performance Improvement of Parallel Processing System through Runtime Adaptation (실행시간 적응에 의한 병렬처리시스템의 성능개선)

  • Park, Dae-Yeon;Han, Jae-Seon
    • Journal of KIISE:Computer Systems and Theory
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    • v.26 no.7
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    • pp.752-765
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    • 1999
  • 대부분 병렬처리 시스템에서 성능 파라미터는 복잡하고 프로그램의 수행 시 예견할 수 없게 변하기 때문에 컴파일러가 프로그램 수행에 대한 최적의 성능 파라미터들을 컴파일 시에 결정하기가 힘들다. 본 논문은 병렬 처리 시스템의 프로그램 수행 시, 변화하는 시스템 성능 상태에 따라 전체 성능이 최적화로 적응하는 적응 수행 방식을 제안한다. 본 논문에서는 이 적응 수행 방식 중에 적응 프로그램 수행을 위한 이론적인 방법론 및 구현 방법에 대해 제안하고 적응 제어 수행을 위해 프로그램의 데이타 공유 단위에 대한 적응방식(적응 입도 방식)을 사용한다. 적응 프로그램 수행 방식은 프로그램 수행 시 하드웨어와 컴파일러의 도움으로 프로그램 자신이 최적의 성능을 얻을 수 있도록 적응하는 방식이다. 적응 제어 수행을 위해 수행 시에 병렬 분산 공유 메모리 시스템에서 프로세서 간 공유될 수 있은 데이타의 공유 상태에 따라 공유 데이타의 크기를 변화시키는 적응 입도 방식을 적용했다. 적응 입도 방식은 기존의 공유 메모리 시스템의 공유 데이타 단위의 통신 방식에 대단위 데이타의 전송 방식을 사용자의 입장에 투명하게 통합한 방식이다. 시뮬레이션 결과에 의하면 적응 입도 방식에 의해서 하드웨어 분산 공유 메모리 시스템보다 43%까지 성능이 개선되었다. Abstract On parallel machines, in which performance parameters change dynamically in complex and unpredictable ways, it is difficult for compilers to predict the optimal values of the parameters at compile time. Furthermore, these optimal values may change as the program executes. This paper addresses this problem by proposing adaptive execution that makes the program or control execution adapt in response to changes in machine conditions. Adaptive program execution makes it possible for programs to adapt themselves through the collaboration of the hardware and the compiler. For adaptive control execution, we applied the adaptive scheme to the granularity of sharing adaptive granularity. Adaptive granularity is a communication scheme that effectively and transparently integrates bulk transfer into the shared memory paradigm, with a varying granularity depending on the sharing behavior. Simulation results show that adaptive granularity improves performance up to 43% over the hardware implementation of distributed shared memory systems.