Browse > Article

Janus-FTL Adjusting the Size of Page and Block Mapping Areas using Reference Pattern  

Kwon, Hun-Ki (서울시립대학교 컴퓨터고학부)
Kim, Eun-Sam (홍익대학교 정보컴퓨터공학부)
Choi, Jong-Moo (단국대학교 컴퓨터학과)
Lee, Dong-Hee (서울시립대학교 컴퓨터고학부)
Noh, Sam-H. (홍익대학교 정보컴퓨터공학부)
Abstract
Naturally, block mapping FTL works well for sequential writes while page mapping FTL does well for random writes. To exploit their advantages, a practical FTL should be able to selectively apply a suitable scheme between page and block mappings for each write pattern. To meet that requirement, we propose a hybrid mapping FTL, which we call Janus-FTL, that distributes data to either block or page mapping areas. Also, we propose the fusion operation to relocate the data from block mapping area to page mapping area and the defusion operation to relocate the data from page mapping area to block mapping area. And experimental results of Janus-FTL show performance improvement of maximum 50% than other hybrid mapping FTLs.
Keywords
Flash memory storage; Page mapping; Block mapping; Garbage collection; FTL (Flash-memory Translation Layer);
Citations & Related Records
연도 인용수 순위
  • Reference
1 Understanding the Flash Translation Layer (FTL) Specification: Intel Corporation, 1998
2 S. Lee. D. Shin, Y.-J. Kim and J. Kim, “LAST: Locality-Aware Sector Translation for NAND Flash Memory-Based Storage Systems,” ACM SIGOPS Operating. Systems Review, vol.42, no.6, pp.36-42, 2008   DOI
3 J. Lee, S. Kim, H. Kwon, C. Hyun, S. Ahn, J. Choi, D. Lee and S. H. Nob, “Block Recycling Schemes and Their Cost-based Optimization in NAND Flash Memory based Storage System,” in Proceedings of 7th ACM & IEEE International Conference on Embedded Software, pp.174-182, 2007   DOI
4 S. W. Lee, D. J. Park, T. S. Chung, D. H. Lee, S. Park and H. J. Song, “A Log Buffer based Flash Translation Layer using Fully Associative Sector Translation,” ACM Transactions on Embedded Computing Systems, vol.6, no.1, Feb., 2007   DOI
5 M. Rosenblum and J. K. Ousterhout, "The Design and Implementation of a Log-Structured File System," ACM Transactions on Computer Systems, vol.10, no.1, pp.26-52, 1992   DOI
6 J. Kim, J. M. Kim, S. H. Noh, S. L. Mm and Y. Cho, “A Space-efficient Flash Translation Layer for CompactFlash Systems,” IEEE Transactions on Consumer Electronics, vol.28, no.2, pp.366-375, 2002   DOI   ScienceOn
7 H. Kim, J. H. Kim, S. Choi et al., “A Page Padding Method for Fragmented Flash Storage,” Lecture Notes in Computer Science, vol. 4705, pp.164-177, 2007   DOI
8 A. Gupta, Y. Kim and B. Urgaonkar, “DFTL: A Flash Translation Layer Employing Demand-Based Selective Caching of Page-Level Address Mappings,” in Proceeding of the 14th International Conference on Architectural Support for Program-ming Languages and Operating Systems, pp.229-240, 2009   DOI
9 1G ${\times}$ 8Bit / 2G ${\times}$8Bit NAND Flash memory (K9L8G08U0M) Data Sheets," Samsung Electronics, Co., 2005