• BMB Reports
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• 제49권4호
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• pp.199-200
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• 2016

Gene regulation in the brain is essential for long-term plasticity and memory formation. Despite this established notion, the quantitative translational map in the brain during memory formation has not been reported. To systematically probe the changes in protein synthesis during memory formation, our recent study exploited ribosome profiling using the mouse hippocampal tissues at multiple time points after a learning event. Analysis of the resulting database revealed novel types of gene regulation after learning. First, the translation of a group of genes was rapidly suppressed without change in mRNA levels. At later time points, the expression of another group of genes was downregulated through reduction in mRNA levels. This reduction was predicted to be downstream of inhibition of ESR1 (Estrogen Receptor 1) signaling. Overexpressing Nrsn1, one of the genes whose translation was suppressed, or activating ESR1 by injecting an agonist interfered with memory formation, suggesting the functional importance of these findings. Moreover, the translation of genes encoding the translational machineries was found to be suppressed, among other genes in the mouse hippocampus. Together, this unbiased approach has revealed previously unidentified characteristics of gene regulation in the brain and highlighted the importance of repressive controls.

• ETRI Journal
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• 제31권6호
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• pp.784-794
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• 2009

We present a full HD (1080p) H.264/AVC High Profile hardware encoder based on fast motion estimation (ME). Most processing cycles are occupied with ME and use external memory access to fetch samples, which degrades the performance of the encoder. A novel approach to fast ME which uses shared multibank memory can solve these problems. The proposed pixel subsampling ME algorithm is suitable for fast motion vector searches for high-quality resolution images. The proposed algorithm achieves an 87.5% reduction of computational complexity compared with the full search algorithm in the JM reference software, while sustaining the video quality without any conspicuous PSNR loss. The usage amount of shared multibank memory between the coarse ME and fine ME blocks is 93.6%, which saves external memory access cycles and speeds up ME. It is feasible to perform the algorithm at a 270 MHz clock speed for 30 frame/s real-time full HD encoding. Its total gate count is 872k, and internal SRAM size is 41.8 kB.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.429-432
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• 2000

The new MPEG-4 video coding standard enables content-based functionalities. In order to support the philosophy of the MPEG-4 visual standard, each frame of video sequences should be represented in terms of video object planes (VOP’s). In other words, video objects to be encoded in still pictures or video sequences should be prepared before the encoding process starts. Therefore, it requires a prior decomposition of sequences into VOP’s so that each VOP represents a moving object. A parallel processing system is required an automatic segmentation to be processed in real-time, because an automatic segmentation is time consuming. This paper addresses the parallel processing: system for an automatic segmentation for separating moving object from the background in image sequences. The proposed parallel processing system comprises of processing elements (PE’s) and a multi-access memory system (MAMS). Multi-access memory system is a memory controller to perform parallel memory access with the variety of types: horizontal, vertical, and block access way. In order to realize these ways, a multi-access memory system consists of a memory module selection module, data routing modules, and an address calculation and routing module. The proposed system is simulated and evaluated by the CADENCE Verilog-XL hardware simulation package.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• 대한전자공학회논문지SD
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• 제47권5호
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• pp.41-47
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• 2010

본 논문에서는 SSD (solid state disk)에 쓰이는 NAND flash 메모리 에러 정정에 관한 오류정정 방법 중에서 Parallel BCH(Bose-Chaudhuri-Hocquenghem) 방법 및 VLSI 설계를 제안하였다. 제안된 설계는 에러 정정 능력(t=18, 8) 을 가변적으로 하여 사용빈도수의 증가로 높은 에러 율을 가진 데이터 공간에 신뢰성을 높였고, 디코더의 병렬처리 비트 수를 인코더의 처리 비트 수에 2배로 하여 디코더의 수행시간을 줄였고 이에 따르는 latency도 기존 회로에 비해 1/2로 감소함을 확인 하였다.

• 아동학회지
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• 제10권1호
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• pp.11-25
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• 1989

The purpose of the present research was to study developmental trends in and relationships between recall, organizational strategy, and metamemory in young children. The subjects were 84 children, 14 boys and 14 girls at each age level, 4, 6, and 8. Two tasks (memory task & metamemory task) were used to assess children's recall, organizational strategy, and metamemory based on Sodian et al.(1986). All subjects were randomly assigned either to the play-and-remember condition or to the sort-and-remember condition. The two tasks were administered to children individually with the memory task followed by the metamemory task. The data were analysed by the statistical methods of two-way ANOVA, Student-Newman-Keuls post hoc test, Mann-Whitney U test, Kruskal-Wallis test, Pearson's correlation coefficient and Kendall's Tau. Children's recall (free, conceptually-cued, and perceptually-cued) level increased with age. There were significant experimental condition differences in free recall and conceptually-cued recall, but not in perceptually-cued recall. Children's organizational strategy showed differential developmental trends by experimental condition. Use of conceptual strategy at both encoding and retrieval increased with age in both experimental conditions. Use of perceptual strategy (PS) at encoding showed an inverted-U age effect in the play-and-remember condition, but PS decreased linearly with age in the sort-and-remember condition. There were significant age differences in metamemory, and there were significant correlations between recall and organizational strategy.

• 제어로봇시스템학회논문지
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• 제15권1호
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• pp.111-119
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• 2009

For daily life interaction with human, robots need the capability of encoding and storing cognitive information and retrieving it contextually. In this paper, spatiotemporal grounding of cognitive information for a language based cognitive system is presented. The cognitive information of the event occurred at a robot is described with a sentence, stored in a memory, and retrieved contextually. Each sentence is parsed, discriminated with the functional type of it, and analyzed with argument structure for connecting to cognitive information. With the proposed grounding, the cognitive information is encoded to sentence form and stored in sentence memory with object descriptor. Sentences are retrieved for answering questions of human by searching temporal information from the sentence memory and doing spatial reasoning in schematic imagery. An experiment shows the feasibility and efficiency of the spatiotemporal grounding for advanced service robot.

• 한국컴퓨터그래픽스학회논문지
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• 제6권4호
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• pp.35-42
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• 2000

3차원 텍스춰 매핑은 얇은 종이를 부자연스럽게 물체에 붙이는 것과는 달리 마치 원래의 재료로부터 조각을 한 것과 같은 매우 자연스러운 시각적 효과를 내는 장점이 있다. 하지만 빠른 텍스춰 매핑을 위하여 샘플링을 통하여 생성한 3차원 텍스춰를 실시간 계산을 위하여 메모리에 올리는 것은 일반적으로 텍스춰의 방대한 크기 때문에 실용적이지 못하다. 최근 [11]에서는 실용적인 실시간 3차원 텍스춰 매핑 기법을 제안하였는데 여기서는 웨이블릿에 기반한 압축 기법을 사용하여 메모리 문제를 해결하려 하였다. 이 논문에서는 이러한 압축 기반 실시간 3D 텍스춰 매핑에 사용될 수 있는 또 다른 압축 기법에 대하여 살펴보았다. 특히 벡터양자화 방법과 FXT1 방법을 3차원 텍스춰 압축에 적합하도록 확장을 하고 그 성능을 비교 분석을 하였다.

• 정보처리학회논문지B
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• 제10B권5호
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• pp.575-578
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• 2003

SPIHT는 수행속도가 빠르고 효율적인 웨이블릿 기반의 이미지 압축 알고리즘으로 잘 알려져 있다. 그러나, SPIHT는 알고리즘 수행에 필요한 제로트리 및 계수의 상태를 저장하기 위하여 리스트 구조를 사용하고 있어 추가 메모리론 요구하며, 비트율의 증가에 따라 메모리 요구량이 증가하는 단점을 가진다. 본 논문에서는 SPIHT 알고리즘을 수행하는데 있어 추가 메모리를 요구하지 않는 MZP-DFS 알고리즘을 제안한다. 제안된 기법은 깊이우선 순서에 따라 공간트리를 탐색하고 테스트 함수 및 복원 계수의 LSB를 이용함으로써 추가 메모리를 제거하였으며 SPIHT와 동일한 성능을 가진다. MZP-DFS는 추가 메모리를 요구하지 않기 때문에 하드웨어 제작비용을 절감할 수 있으며, 각각의 공간트리를 병렬적으로 수행할 수 있기 때문에 실시간 이미지 압축에 적합하다.

• 한국정보과학회논문지:시스템및이론
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• 제31권5_6호
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• pp.321-327
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• 2004

SPIHT는 수행속도가 빠르고 효율적인 웨이블릿 기반의 이미지 압축 알고리즘으로 잘 알려져 있다. 그러나, SPIHT는 알고리즘을 수행하는 과정에서 발생하는 제로트리 및 계수의 상태를 저장하기 위하여 리스트 구조를 사용하고 있어 추가 메모리를 요구하며, 비트율의 증가에 따라 메모리 요구량이 증가하는 단점을 가진다. 본 논문에서는 SPIHT 알고리즘을 수행하는데 있어 추가 메모리를 요구하지 않는 MZC-BFS 알고리즘을 제안한다. 제안된 기법은 peano 코드를 이용하여 완벽한 너비우선 순서에 따라 공간트리를 탐색하며, 부호화 과정에서 이전상태 중요계수 테스트 및 복원과정에서 계수의 LSB를 이용함으로써 SPIHT에서 리스트 문제를 제거한다. MZC-BFS는 SPIHT에 비하여 리스트를 사용하지 않기 때문에 하드웨어 구현이 간단하고 수행속도가 빠를 뿐 아니라 추가 메모리를 요구하지 않기 때문에 하드웨어 제작비용을 절감할 수 있다.