• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.156-160
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• 2006

Capacitance versus voltage (C-V) curves of Ge-nanocrystal (NC)-embedded MOS capacitors with and without a single capping Al2O3 layer are characterized in this work. C-V curves of the Ge-NC-embedded MOS capacitor with the A12O3 layer are counterclockwise in the voltage sweeps, which indicates tile presence of charge storages in the Ge NCs by the tunnelling of charge carriers between the Si substrate and the Ge NCs. In the Ge-NC-embedded MOS capacitor without Al2O3 layer, clockwise hysteresis of the C-V curves and leftward shifts of the flat band voltages are observed for the embedded MOS capacitor without the Al2O3 layer. It is suggested that the characteristics of the C-V curves are due to the charge trapping at oxygen vacancies within a SiO2 layer. In addition, the illumination of the white light enhances the lower capacitance part of the C-V hysteresis. The origin for the enhancement is discussed in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.132-138
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• 2003

We investigated the polarization retention characteristics of ferroelectric capacitors with $Pb(Zr,Ti)O_3$ (PZT) thin films which were fabricated by different deposition methods. In thermally-accelerated retention tests, PZT films which were prepared by a chemical solution deposition (CSD) method showed rapid decay of retained polarization charges as the thickness of the films decreased down to 100 nm, while the films which were grown by metal organic chemical vapor deposition (MOCVD) retained relatively large non-volatile charges at the corresponding thickness. We concluded that in the CSD-grown films, the thicker interfacial passive layer compared with the MOCVD-grown films had an unfavorable effect on retention behavior. We observed the existence of such interfacial layers by extrapolation of the total capacitance with thickness of the films and the capacitance of these layers was larger in MOCVD-grown films than in CSD-grown films. Due to incomplete compensation of surface polarization charges by the free charges in the metal electrodes, the interfacial field activated the space charges inside the interfacial layers and deposited them at the boundary between the ferroelectric layer and the interfacial layer. Such space charges built up an internal field inside the films, which interfered with domain wall motion, so that retention property at last became degraded. We observed less imprint which was a result of less internal field in MOCVD-grown films while large imprint was observed in CSD-grown films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• The Korean Journal of Ceramics
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• v.6 no.2
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• pp.138-142
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• 2000

Thin film $LiNbO_3$MFS (metal-ferroelectric-semiconductor) capacitor showed improved characteristics such as low interface trap density, low interaction with Si substrate, and large remanent polarization. This paper reports ferroelectric $LiNbO_3$thin films grown directly on p-type Si (100) substrates by 13.56 MHz RF magnetron sputtering system for FRAM (ferroelectric random access memory) applications. RTA (rapid thermal anneal) treatment was performed for as-deposited films in an oxygen atmosphere at $600^{\circ}C$ for 60sec. We learned from X-ray diffraction that the RTA treated films were changed from amorphous to poly-crystalline $LiNbO_3$which exhibited (012), (015), (022), and (023) plane. Low temperature film growth and post RTA treatments improved the leakage current of $LiNbO_3$films while keeping other properties almost as same as high substrate temperature grown samples. The leakage current density of $LiNbO_3$films decreased from $10^{-5}$ to $10^{-7}$A/$\textrm{cm}^2$ after RTA treatment. Breakdown electric field of the films exhibited higher than 500 kV/cm. C-V curves showed the clockwise hysteresis which represents ferroelectric switching characteristics. Calculated dielectric constant of thin film $LiNbO_3$illustrated as high as 27.9. From ferroelectric measurement, the remanent polarization and coercive field were achieved as 1.37 $\muC/\textrm{cm}^2$ and 170 kV/cm, respectively.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.27-32
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• 1999

Metal-ferroelectric-semiconductor devices by susing rapid thermal annealed $LiNbO_3/Si$(100) structures were fabricated and demonstrated nonvolatile memory operations. The estimated field-effect electron mobility and transconductance on a linear region of the fabricated FET were about $600cm^2/V{\cdot}s$ and 0.16mS/mm, respectively. The ID-VG characteristics of MFSFET's showed a hysteresis loop due to the ferroelectric nature of the $LiNbO_3 films. The drain current of the on state was more than 4 orders of magnitude larger than the off state current at the same read gate voltage of 0.5V, which means the memory operation of the MFSFET. A write voltage as low as ${\pm}3V$, which is applicable to low power integrated circuits, was used for polarization reversal. The ferroelectric capacitors showed no polarization degradation up to $10^{10}$ switching cycles with the application of symmetric bipolar voltage pulse (peak-to-peak 6V, 50% duty cycle) of 500kHz.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.58-61
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• 2001

Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

• Electrical & Electronic Materials
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• v.11 no.10
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• pp.46-52
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• 1998

In this study, polarization switching characteristics of Pb(ZrxTil-x)O3 (PZT) thin films were investigated. Switching times(ts) were found to be decreased as the Zr mol% was increased. But, the switching peak currents(Imax) showed the largest value at 50 mol% Zr. As a result of this experiment, ts was found to be depended on the remanent polarization and coercive field and also Imax strongly depended on the dielectric constant of PZT thin films. In order to investigate the partial switching kinetics of PZT thin films, short and relatively small voltage pulses were applied to the MFM(metalferroelectric metal) PZT capacitors and polarization switching curves were measured with a variation of the total width of the applied pulses. Also, the switching curves were measured at different applied voltages(4, 8, 10, 12 and 14 volts). As the applied voltages increased, ts and Imax were found to be decreased and increased, respectively. In case of fatigued specimen which we applied $\pm$10 volts square pulse for 1010 cycles, ts and Imax were found to be shorter and smaller than those of virgin specimens. This is due to the decrease of the remanent polarization and the increase of the coercive field.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.149-149
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• 2008

Metal-Insulator-Metal(MIM) capacitors have been studied extensively for next generation of high-density dynamic random access memory (DRAM) devices. Of several candidates for metal electrodes, Ru or its conducting oxide $RuO_2$ is the most promising material due to process maturity, feasibility, and reliability. ALD can be used to form the Ru and RuO2 electrode because of its inherent ability to achieve high level of conformality and step coverage. Moreover, it enables precise control of film thickness at atomic dimensions as a result of self-limited surface reactions. Recently, ALD processes for Ru and $RuO_2$, including plasma-enhanced ALD, have been studied for various semiconductor applications, such as gate metal electrodes, Cu interconnections, and capacitor electrodes. We investigated Ru/$RuO_2$ thin films by thermal ALD with various deposition parameters such as deposition temperature, oxygen flow rate, and source pulse time. Ru and $RuO_2$ thin films were grown by ALD(Lucida D150, NCD Co.) using RuDi as precursor and O2 gas as a reactant at $200\sim350^{\circ}C$.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.87-89
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• 2005

$Bi_{3.25}Y_{0.75}Ti_{3}O_{12}$[BYT] ferroelectric thin films were deposited by RF-Sputtering method on the $Pt/Ti/SiO_2/Si$. We investigated the effects of processing condition (especially post-annealing) on the structural and ferroelectric properties of the BYT thin films. Increasing the annealing temperature, the peak intensity of (117) increased and c-axis orientation decreased. The BYT thin films crystallized well at $600^{\circ}C$ for 30min. No secondary phases observed in the XRD pattern. At annealing temperature of $700^{\circ}C$, the thin films had no cracks and the grain was uniform. The calculated lattice constants of BYT thin films were a=0.539nm, b=0.536nm, c=3.288nm. The remnant polarization of the $Bi_{3.25}Y_{0.75}Ti_{3}O_{12}$ capacitor reached $1.8uC/cm^2$ at an applied field about 400kV/cm. The BYT thin films can be used as capacitors in Ferroelectric Random Access Memory device.