• Title/Summary/Keyword: Memory allocation

Search Result 205, Processing Time 0.022 seconds

Design of an Automated Testing Tool to Detect Dynamic Memory Access Errors in C Programs (C언어 기반 프로그램의 동적 메모리 접근 오류 테스트 자동화 도구 설계)

  • Cho, Dae-Wan;Oh, Seung-Uk;Kim, Hyeon-Soo
    • Journal of KIISE:Software and Applications
    • /
    • v.34 no.8
    • /
    • pp.708-720
    • /
    • 2007
  • Memory access errors are frequently occurred in computer programs written in C programming language [1,2]. Accordingly, a number of research works have suggested a wide variety of methods to detect such errors automatically. However, they have one or more of the following problems: inability to detect all memory errors, changing the memory allocation mechanism, and excessive performance overhead. To cope with these problems, in this paper we suggest a new and automated tool to detect dynamic memory access errors in C programs.

Block-based Adaptive Bit Allocation for Reference Memory Reduction (효율적인 참조 메모리 사용을 위한 블록기반 적응적 비트할당 알고리즘)

  • Park, Sea-Nae;Nam, Jung-Hak;Sim, Dong-Gy;Joo, Young-Hun;Kim, Yong-Serk;Kim, Hyun-Mun
    • Journal of the Institute of Electronics Engineers of Korea SP
    • /
    • v.46 no.3
    • /
    • pp.68-74
    • /
    • 2009
  • In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm can obtain around 1.7% BD-bitrate gain and 0.03dB BD-PSNR gain, compared with the conventional fixed-bit min-max algorithm with 37.5% memory saving.

Efficient Resource Allocation Algorithm for Multiuser OFDM Systems (다중 사용자 OFDM 시스템에서의 효율적인 자원 할당 알고리즘)

  • Lee, Jung-Yoon;Yoon, Dong-Weon;Park, Sang-Kyu
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.32 no.4A
    • /
    • pp.344-350
    • /
    • 2007
  • Start after striking space key 2 times. Lately, a lot of researches have been done on the resource allocation for multiuser OFDM(Orthogonal Frequency Division Multiplexing) systems due to its spectral efficiency for high-rate multimedia data services. For multimedia services in which every user is guaranteed to have minimum required bit rate and bit error probability, it is critical to utilize the limited resources efficiently to improve the performance of the system. The introduced allocation method improves spectral efficiency to use the left subcarriers in Zhang's algorithm. By using this method, the system can provide services to more users constantly, except for a bit increasing complexity and memory for deciding the left subcarriers and reallocating the subcarriers.

Design of an Automatic Synthesis System for Datapaths Based on Multiport Memories (다중포트 메모리를 지원하는 데이터패스 자동 합성 시스템의 설계)

  • 이해동;김용노;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.31A no.7
    • /
    • pp.117-124
    • /
    • 1994
  • In this pape, we propose a graph-theoretic approach for solving the allocation problem for the synthesis of datapaths based on multiport memories. An efficient algorithm is devised by using the weighted bipartite matching algorithm to assign variables to each port of memory modules. The proposed algorithm assigns program variables into a minimum number of multiport memory modules such that usage of memory elements and interconnection cost can be kept minimal. Experimental results show that the proposed algorithm generates the datapaths with fewer registers in memory modules and less interconnection cost for several benchmarks available from the literatures.

  • PDF

Escape Analysis for Stack Allocation in Java (자바 객체의 스택 저장 가능성 판별을 위한 정적 분석 기법)

  • 조은선
    • Journal of KIISE:Software and Applications
    • /
    • v.31 no.6
    • /
    • pp.840-848
    • /
    • 2004
  • Garbage collecting objects in Java makes memory management easier for the programmer, but it is time consuming. Stack allocation may be an alternative which identifies stack-allocatable objects before the execution, without performance degradation. We suggest an escaping analysis recording the interprocedural movement of the method, to detect an object the method of whose creation may have been already deactivated during the access. Our approach is different from prior works, enables us to handle some cases that are missed in the previous variable - oriented approach.

Enhancing the Performance of Multiple Parallel Applications using Heterogeneous Memory on the Intel's Next-Generation Many-core Processor (인텔 차세대 매니코어 프로세서에서의 다중 병렬 프로그램 성능 향상기법 연구)

  • Rho, Seungwoo;Kim, Seoyoung;Nam, Dukyun;Park, Geunchul;Kim, Jik-Soo
    • Journal of KIISE
    • /
    • v.44 no.9
    • /
    • pp.878-886
    • /
    • 2017
  • This paper discusses performance bottlenecks that may occur when executing high-performance computing MPI applications in the Intel's next generation many-core processor called Knights Landing(KNL), as well as effective resource allocation techniques to solve this problem. KNL is composed of a host processor to enable self-booting in addition to an existing accelerator consisting of a many-core processor, and it was released with a new type of on-package memory with improved bandwidth on top of existing DDR4 based memory. We empirically verified an improvement of the execution performance of multiple MPI applications and the overall system utilization ratio by studying a resource allocation method optimized for such new many-core processor architectures.

RRAM (Redundant Random Access Memory) Spare Allocation in Semiconductor Manufacturing for Yield Improvement (수율향상을 위한 반도체 공정에서의 RRAM (Redundant Random Access Memory) Spare Allocation)

  • Han, Young-Shin
    • Journal of the Korea Society for Simulation
    • /
    • v.18 no.4
    • /
    • pp.59-66
    • /
    • 2009
  • This has been possible by integration techniques such as very large scale integration (VLSI) and wafer scale integration (WSI). Redundancy has been extensively used for manufacturing memory chips and to provide repair of these devices in the presence of faulty cells. If there are too many defects, the momory has to be rejected. But if there are a few defects, it will be more efficient and cost reducing for the company to use it by repairing. Therefore, laser-repair process is nedded for such a reason and redundancy analysis is needed to establish correct target of laser-repair process. The proposed CRA (Correlation Repair Algorithm) simulation, beyond the idea of the conventional redundancy analysis algorithm, aims at reducing the time spent in the process and strengthening cost competitiveness by performing redundancy analysis after simulating each case of defect.

EPET-WL: Enhanced Prediction and Elapsed Time-based Wear Leveling Technique for NAND Flash Memory in Portable Devices

  • Kim, Sung Ho;Kwak, Jong Wook
    • Journal of the Korea Society of Computer and Information
    • /
    • v.21 no.5
    • /
    • pp.1-10
    • /
    • 2016
  • Magnetic disks have been used for decades in auxiliary storage devices of computer systems. In recent years, the use of NAND flash memory, which is called SSD, is increased as auxiliary storage devices. However, NAND flash memory, unlike traditional magnetic disks, necessarily performs the erase operation before the write operation in order to overwrite data and this leads to degrade the system lifetime and performance of overall NAND flash memory system. Moreover, NAND flash memory has the lower endurance, compared to traditional magnetic disks. To overcome this problem, this paper proposes EPET (Enhanced Prediction and Elapsed Time) wear leveling technique, which is especially efficient to portable devices. EPET wear leveling uses the advantage of PET (Prediction of Elapsed Time) wear leveling and solves long-term system failure time problem. Moreover, EPET wear leveling further improves space efficiency. In our experiments, EPET wear leveling prolonged the first bad time up to 328.9% and prolonged the system lifetime up to 305.9%, compared to other techniques.

A Review of Data Management Techniques for Scratchpad Memory (스크래치패드 메모리를 위한 데이터 관리 기법 리뷰)

  • DOOSAN CHO
    • The Journal of the Convergence on Culture Technology
    • /
    • v.9 no.1
    • /
    • pp.771-776
    • /
    • 2023
  • Scratchpad memory is a software-controlled on-chip memory designed and used to mitigate the disadvantages of existing cache memories. Existing cache memories have TAG-related hardware control logic, so users cannot directly control cache misses, and their sizes are large and energy consumption is relatively high. Scratchpad memory has advantages in terms of size and energy consumption because it eliminates such hardware overhead, but there is a burden on software to manage data. In this study, data management techniques of scratchpad memory were classified and examined, and ways to maximize the advantages were discussed.

A dual-link CC-NUMA System Tolerant to the Multiprogramming Environment (다중 프로그램 환경에 적합한 이중 연결 CC-NUMA 시스템)

  • Suh, Hyo-Joong
    • The KIPS Transactions:PartA
    • /
    • v.11A no.3
    • /
    • pp.199-206
    • /
    • 2004
  • Under the multiprogrammed situation, the performance of multiprocessor system is affected by the process allocation policy of the operating systems. The lowest communication cost can be achieved when the related processes positioned to the adjacent processors. While the effective allocation is quite difficult to the real situation, and the processing of the allocation policy consumes some computation time. The dual-ring CC-NUMA systems exhibit a quite performance difference according to the process a1location policy due to a lot of unbalanced memory transactions on the interconnection networks. In this paper, I propose a load balanced dual-link CC-NUMA system that does not requires the processes allocation policy. By the program-driven simulation results. the proposed system shows no remarkable difference according to the allocation policy while the dual-ring systems shows 10% performance improvement by the process allocation. In addition, the proposed system outperforms the dual~ring systems about 1.5 times.