• Geophysics and Geophysical Exploration
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• v.14 no.1
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• pp.98-104
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• 2011

Numerical simulation in exploration geophysics provides important insights into subsurface wave propagation phenomena. Although elastic wave simulations take longer to compute than acoustic simulations, an elastic simulator can construct more realistic wavefields including shear components. Therefore, it is suitable for exploration of the responses of elastic bodies. To overcome the long duration of the calculations, we use a Graphic Processing Unit (GPU) to accelerate the elastic wave simulation. Because a GPU has many processors and a wide memory bandwidth, we can use it in a parallelised computing architecture. The GPU board used in this study is an NVIDIA Tesla C1060, which has 240 processors and a 102 GB/s memory bandwidth. Despite the availability of a parallel computing architecture (CUDA), developed by NVIDIA, we must optimise the usage of the different types of memory on the GPU device, and the sequence of calculations, to obtain a significant speedup of the computation. In this study, we simulate two- (2D) and threedimensional (3D) elastic wave propagation using the Finite-Difference Time-Domain (FDTD) method on GPUs. In the wave propagation simulation, we adopt the staggered-grid method, which is one of the conventional FD schemes, since this method can achieve sufficient accuracy for use in numerical modelling in geophysics. Our simulator optimises the usage of memory on the GPU device to reduce data access times, and uses faster memory as much as possible. This is a key factor in GPU computing. By using one GPU device and optimising its memory usage, we improved the computation time by more than 14 times in the 2D simulation, and over six times in the 3D simulation, compared with one CPU. Furthermore, by using three GPUs, we succeeded in accelerating the 3D simulation 10 times.

• Journal of Information Technology Services
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• v.12 no.4
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• pp.369-380
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• 2013

The advent of the state-of-the-art technologies such as cloud computing and big data processing stimulates the provision of various new IT services, which implies that more servers are required to support them. However, the need for more servers will lead to more energy consumption and the efficient use of energy in the computing environment will become more important. The next generation nonvolatile RAM has many desirable features such as byte addressability, low access latency, high density and low energy consumption. There are many approaches to adopt them especially in the area of the file system involving storage devices, but their focus lies on the improvement of system performance, not on energy reduction. This paper suggests a novel approach for energy reduction in which the MRAM-based SSD is utilized as a storage device instead of the hard disk and a downsized page is adopted instead of the 4KB page that is the size of a page in the ordinary file system. The simulation results show that energy efficiency of a new approach is very effective in case of accessing the small number of bytes and is improved up to 128 times better than that of NAND Flash memory.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.419-422
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• 2004

A sensing scheme for current-mode magneto-resistance random access memory (MRAM) with a 1T1MTJ cell structure is proposed. Magnetic tunnel junction (MTJ) resistance, which is HIGH or LOW, is converted to different cell currents during READ operation. The cell current is then amplified to be evaluated by the reference cell current. In this scheme, conventional bit line sense amplifiers are not required and the operation is less sensitive to voltage noise than that of voltage-mode circuit is. It has been confirmed with HSPICE simulations using a 0.35-${\mu}m$ 2-poly 4-metal CMOS technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05b
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• pp.74-77
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• 2002

Ferroelectric Random Access Memory(FRAM) and MEMS applications require noble metal or refractory metal oxide electrodes. In this study, Ru thin films were etched using $O_2$+10% $CF_4$ plasma in an inductively coupled plasma(ICP) etching system. The etch rate of Ru thin films was examined as function of rf power, DC bias applied to the substrate. The enhanced etch rate can be obtained not only with increasing rf power and DC bias voltage, but also with small addition $CF_4$ gas. The selectivity of $SiO_2$ over Ru are 1.3. Radical densities of oxygen and fluorine in $CF_4/O_2$ plasma have been investigated by optical emission spectroscopy(OES). The etching profiles of Ru films with an photoresist pattern were measured by a field emission scanning electron microscope (FE-SEM). The additive gas increases the concentration of oxygen radicals, therefore increases the etch rate of the Ru thin films and enhances the etch slope. In $O_2$+10% $CF_4$ plasma, the etch rate of Ru thin films increases up to 10% $CF_4$ but decreases with increasing $CF_4$ mixing ratio.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.375-381
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• 2001

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide bit-line with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance tungsten bit-line fabrication process with various RTP(Rapid Thermal Process) temperature and additional ion implantation. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF$_2$ ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.15.2-15.2
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• 2011

비휘발성 저항 메모리소자인 resistance random access memory (ReRAM)는 간단한 소자구조와 빠른 동작특성을 나타내며 고집적화에 유리하기 때문에 차세대 메모리소자로써 각광받고 있다. 현재, 이성분계 산화물, 페로브스카이트 산화물, 고체 전해질 물질, 유기재료 등을 응용한 저항 메모리소자에 대한 연구가 활발히 진행되고 있다. 그 중 ZnO를 기반으로 하는 amorphous InGaZnO (a-IGZO) 박막은 active layer 로써 박막트랜지스터 적용 시 우수한 전기적 특성을 나타내며, 빠른 동작특성과 높은 저항 변화율을 보이기 때문에 ReRAM 에 응용 가능한 재료로써 기대되고 있다. 또한 가시광선 영역에서 광학적으로 투명한 특성을 보이기 때문에 투명소자로서도 응용이 기대되고 있다. 본 연구에서는 indium tin oxide (ITO) 투명 전극을 적용한 ITO/a-IGZO/ITO 구조의 투명 소자를 제작하여 저항 메모리 특성을 평가하였다. Radio frequency (RF) sputter를 이용하여 IGZO 박막을 합성하고, ITO 전극을 증착하여 투명 저항 메모리소자를 구현하였고, resistive switching 효과를 관찰하였다. 또한, 열처리를 통해 a-IGZO 박막 내의 Oxygen vacancy와 같은 결함의 정도에 따른 on/off 저항의 변화를 관찰할 수 있었다. 제작된 저항 메모리소자는 unipolar resistive switching 특성을 보였으며, 높은 on/off 저항의 차이를 유지하였다. Scanning electron microscope (SEM)을 통해 합성된 박막의 형태를 평가하였고, X-ray diffraction (XRD) 및 transmission electron microscopy (TEM)을 통해 결정성을 평가하였다. 제작된 소자의 전기적 특성은 HP-4145 를 이용하여 측정하고 비교 분석하였다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.125-125
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• 2003

PZT(Pb(Zr,Ti)O3)는 우수한 강유전 특성을 가지기 때문에 FRAM (Ferroelectric Random Access Memory) 소자에 응용하기 위해 많은 연구가 진행되고 있다. 스퍼터에 의해 증착된 PZT는 처음에 pyrochlore상으로 존재하다가 후 열처리를 통해 이력 특성을 나타내는 perovskite상으로 천이된다. 일반적인 furnace열처리 방법은 고온에서의 장시간 열처리가 요구되고 Pb-loss현상이나 TiO2와 같은 이차상의 생성 그리고 하부 Pt전극의 roughness증가 및 crack과 같은 문제점이 있다. 최근 들어 후 열처리를 RTA로 이용하는 연구가 진행되고 있는데 이는 열처리 시간이 짧기 때문에 위와 같은 문제점을 개선할 수 있었다. 하지만 RTA방법 또한 어느 정도의 thermal budget이 존재하고 추가적 장비가 필요하며 기판의 전체적 가열공정이므로 다른 CMOS공정과 compatibility가 떨어진다. 따라서 본 실험에서는 위와 같은 문제를 해결하고자 노력을 집중하였고 이를 위한 새로운 열처리 방법을 개발하였다. 즉 Pt 하부전극에 전압(전류)을 인가하여 순간적으로 고온으로 결정화시키는 새로운 공정을 모색하였는데 이와 같은 방법은 열처리를 위한 추가적인 장비가 필요없고 국부적으로 순간적인 가열이기 때문에 glass기판에도 적합하며 RTA보다 승온시간 및 열처리 시간이 짧기 때문에 thermal budget도 줄일 수 있었다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.29-32
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• 2000

Cerium oxide thin film has been proposed as a buffer layer between the ferroelectric film and the Si substrate in Metal-Ferroelectric-Insulator-Silicon (MFIS ) structures for ferroelectric random access memory (FRAM) applications. In this study, CeO$_2$thin films were etched with Cl$_2$/Ar gas combination in an inductively coupled plasma (ICP). The highest etch rate of CeO$_2$film is 230 $\AA$/min at Cl$_2$/(Cl$_2$+Ar) gas mixing ratio of 0.2. This result confirms that CeO$_2$thin film is dominantly etched by Ar ions bombardment and is assisted by chemical reaction of Cl radicals. The selectivity of CeO$_2$to YMnO$_3$was 1.83. As a XPS analysis, the surface of etched CeO$_2$thin films was existed in Ce-Cl bond by chemical reaction between Ce and Cl. The results of XPS analysis were confirmed by SIMS analysis. The existence of Ce-Cl bonding was proven at 176.15 (a.m.u.).

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.21-24
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• 2000

Ferroelectric YMnO$_3$thin films are excellent dielectric materials for high integrated ferroelectric random access memory (FRAM) with metal-ferroelectric-silicon field effect transistor (MFSFET) structure. In this study, YMnO$_3$thin films were etched with Cl$_2$/Ar gas chemistries in inductively coupled plasma (ICP). The maximum etch rate of YMnO$_3$thin films is 285 $\AA$/min under Cl$_2$/Ar of 10/0, 600 W/-200 V and 15 mTorr. The selectivities of YMnO$_3$over CeO$_2$and $Y_2$O$_3$are 2.85, 1.72, respectively. The results of x-ray photoelectron spectroscopy (XPS) reflect that Y is removed dominantly by chemical reaction between Y and Cl, while Mn is removed more effective by Ar ion bombardment than chemical reaction. The results of secondary ion mass spectrometer (SIMS) were equal to these of XPS. The etch profile of the etched YMnO$_3$film is approximately 65$^{\circ}$and free of residues at the sidewall.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.