• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.461-476
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• 2003

Due to the implementation ease and alleviation of memory bottleneck effect, NUMA architecture has dominated in the multiprocessor systems for the past several years. However, because the NUMA system distributes memory in each node, frequent remote memory access is a key factor of performance degradation. Therefore, efficient design of RAC(Remote Access Cache) in NUMA system is critical for performance improvement. In this paper, we suggest Multi-Grain RAC which can adaptively control the RAC line size, with respect to each application behavior Then we simulate NUMA system with multi-grain RAC using MINT, event-driven memory hierarchy simulator. and analyze the performance results. At first, with profile-based determination method, we verify the optimal RAC line size for each application and, then, we compare and analyze the performance differences among NUMA systems with normal RAC, with optimal line size RAC, and with multi-grain RAC. The simulation shows that the worst case can be always avoided and results are very close to optimal case with any combination of application and RAC format.

• Proceedings of the Korean Society of Computer Information Conference
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• 2013.01a
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• pp.195-196
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• 2013

본 논문에서는 NVRAM(Non-volatile Random Access Memory) 주 기억장치를 위한 메모리 컨트롤러를 설계한다. NVRAM의 비 휘발성과 낮은 정적 에너지 소모의 장점을 활용하는 한편, 상대적으로 느린 읽기/쓰기 속도 및 큰 쓰기 전력 소모를 개선하기 위해 새로운 캐시 구조를 제안한다. FPGA를 활용하여 Block RAM 128KB 1차 캐시, 16KB 2차 캐시 및 캐시 컨트롤러를 포함하는 메모리 컨트롤러를 구현하였고 NVRAM은 FeRAM를 사용하였다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.23-32
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• 1998

In this paper, we propose a memory compiler to genrate embedded RAMs and ROMs for ASIC chips. We design the leaf cells to be compsoed of memory blocks. The compiler is built using tile-based method to simplify routing. The compiler can genrate any memory layouts to satisfy 64 to 4096 words and 4 to 256 bits per word. The technology we used here is 0.8.mu.m single poly double metal CMOS process. The address access time and power consumption are verifie dthrough the HSPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.23-33
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• 1996

The exploitation of locality of reference in shared memory NUMA multiprocessors is one of the improtant problems in parallel processing today. In this paper, we propose a revised hardeare reference counter to help operating system to manage locality. In contrast to the previous one, the value of counter can abe adjusted dynamically and periodically to adapt the page replication policy to the various memory reference patterns of processors. We use execution-driven simulation of real applications to evaluate the effectiveness of our adjustable DELAY counter. Our main conclusijon is that by using the adjustable DELAY counter the t normalized average memory access costs and the variance of them become smaller for most applications than the previous one and more robust memory management policies can be provided for the operating systems.

• Journal of the Korean Society for Railway
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• v.11 no.2
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• pp.126-138
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• 2008

This paper proposes the preservation method that can effectively process short messages at mobilePOST SMSC(Short Message Service Center) platform on CDMA(Code Division Multiple Access). There are three techniques for the preservation method. First one is shared memory technique where several processes within the system share same memory to process transmission of short messages with maximum performance. Second one is to back-up messages in shared memory to the file system to prevent lost during system initialization or other unstable period. Third technique is that when transmission of short message was completed, finished message is moved from the shared memory to relational database for accounting purposes.

• Journal of electromagnetic engineering and science
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• v.9 no.3
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• pp.152-158
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• 2009

We have developed a novel digital feedback predistortion(DFBPD) linearization based on RF feedback PD for the wide bandwidth modulated signals. The wideband PD operation is carried out by combining the DFBPD and memory lookup table(LUT). To experimentally demonstrate the linearization performance of the proposed PD technique for wideband signal, a class-AB amplifier using an LDMOSFET MRF6S23140 with 140-W peak envelope power is employed at 2.345 GHz. For a forward-link 2FA wideband code-division multiple-access signal with 10 MHz carrier spacing, the proposed DFBPD with memory LUT delivers the adjacent channel leakage ratio at an 10 MHz offset of -56.8 dBc, while those of the amplifier with and without DFBPD are -43.2 dBc and -41.9 dBc, respectively, at an average output power of 40 dBm. The experimental result shows that the new DFBPD with memory LUT provides a good linearization performance for the signal with wide bandwidth.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.211-218
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• 2001

In this paper, we propose the structure of utilizing the memory map, which is using not conventional DRAM but SDRAM, for the hardware implementation of frame memory interface module to the video encoder. As reducing the size of memory map and interface buffer within the same bus, the hardware complexity is improved and the hardware size is minimized as simplifying the interface logic. The conventional system is wasted access time, because of accessing randomly stored data in order to store and output the memories in macro-block unit. therefore the method, which is proposed in this paper, can be effectively reducing the access time of memory, because of the data is stored and processed by line unit.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.169-176
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• 2017

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.55-61
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• 2000

This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.285-291
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• 2010

Flash memory has many good features such as small size, shock-resistance, and low power consumption, but the cost of flash memory is still high to substitute for hard disk entirely. Recently, some mobile devices, such as laptops, attempt to use both flash memory and hard disk together for taking advantages of merits of them. However, existing OSs (Operating Systems) are not optimized to use the heterogeneous storage media. This paper presents a new buffer cache management scheme. First, we allocate buffer cache space according to access patterns of block references and the characteristics of storage media. Second, we prefetch data blocks selectively according to the location of them and access patterns of them. Third, we moves destaged data from buffer cache to hard disk or flash memory considering the access patterns of block references. Trace-driven simulation shows that the proposed schemes enhance the buffer cache hit ratio by up to 29.9% and reduce the total I/O elapsed time by up to 49.5%.