• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2003.03a
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• pp.50-58
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• 2003

We have developed a locally variable time-step scheme matching with discontinuous grids in the flute-difference method for the efficient simulation of seismic wave propagation. The first-order velocity-stress formulations are used to obtain the spatial derivatives using finite-difference operators on a staggered grid. A three-times coarser grid in the high-velocity region compared with the grid in the low-velocity region is used to avoid spatial oversampling. Temporal steps corresponding to the spatial sampling ratio between both regions are determined based on proper stability criteria. The wavefield in the margin of the region with smaller time-step are linearly interpolated in time using the values calculated in the region with larger one. The accuracy of the proposed scheme is tested through comparisons with analytic solutions and conventional finite-difference scheme with constant grid spacing and time step. The use of the locally variable time-step scheme with discontinuous grids results in remarkable saving of the computation time and memory requirement with dependency of the efficiency on the simulation model. This implies that ground motion for a realistic velocity structures including near-surface sediments can be modeled to high frequency (several Hz) without requiring severe computer memory

• Journal of the Korea Society of Computer and Information
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• v.14 no.4
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• pp.9-17
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• 2009

In this paper, we propose a dynamic load distribution technique at the operating system level in mobile storage systems with a heterogeneous storage pair of a small form-factor and disk and a flash memory, which aims at saving energy consumption as well as enhancing I/O performance. Our proposed technique takes a combinatory approach of file placement and buffer cache management techniques to find how the load can be distributed in an energy and performance-aware way for a heterogeneous mobile storage air of a hard disk and a flash memory. We demonstrate that the proposed technique provides better experimental results with heterogeneous mobile storage devices compared with the existing techniques through extensive simulations.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.332-335
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• 2008

In this paper, based on H-tree, which is proposed as the basic data cube structure for multi-dimensional data stream analysis, we have done some analysis. We find there are a lot of redundant nodes in H-tree, and the tree-build method can be improved for saving not only memory, but also time used for inserting tuples. Also, to facilitate more fast and large amount of data stream analysis, which is very important for stream research, H^*-tree is designed and developed. Our performance study compare the proposed H^*-tree and H-tree, identify that H^*-tree can save more memory and time during inserting data stream tuples.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.293-303
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• 2008

As the computing environment moves to the wireless and handheld system, the power efficiency is getting more important. That is the case especially in the embedded hand-held system and the power consumed by the memory system takes the second largest portion in overall. To save energy consumed in the memory system we can utilize low power mode of SDRAM. In the case of RDRAM, nap mode consumes less than 5% of the power consumed in active or standby mode. However hardware controller itself can't use this facility efficiently unless the operating system cooperates. In this paper we focus on how to minimize the number of active units of SDRAM. The operating system allocates its physical pages so that only a few units of SDRAM need to be activated and the unnecessary SDRAM can be put into nap mode. This work can be considered as a generalized and system-wide version of PAVM(Power-Aware Virtual Memory) research. We take all the physical memory into account, especially buffer cache, which takes an half of total memory usage on average. Because of the portion of buffer cache and its importance, PAVM approach cannot be robust without taking the buffer cache into account. In this paper, we analyze the RAM usage and propose power-aware page allocation policy. Especially the pages mapped into the process' address space and the buffer cache pages are considered. The relationship and interactions of these two kinds of pages are analyzed and exploited for energy saving.

• Journal of Advanced Marine Engineering and Technology
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• v.33 no.8
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• pp.1254-1260
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• 2009

CDMA tele-Controller system is designed with a low power consumption 8 bit microcontroller, ATmega 2560. ATmega 2560 microcontroller consists of 4 UART (Universal asynchronous receiver/transmitter) ports, 4 kbytes EEPROM, 256 kbytes flash memory, 4 kbytes SRAM. 4 URAT is used for CDMA modem, communication for GPS module, EEPROM is used for saving a configuration for program running, a flash memory of 256 kbytes is used for storing a F/W(Firm Ware), and SRAM is used for stack, storing memory of global variables while program running. We have tested the communication distance between the coast station and sea by the fabricated control board using 800 MHz CDMA modem and GPS module, which is building for the navigational aid management system by remote control. As a results, the receiving signal strength is above -80 dBm, and then the characteristics of the control board implemented more than 10 km in the distance of the communication.

• Journal of Advanced Marine Engineering and Technology
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• v.35 no.6
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• pp.842-848
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• 2011

A fabricated hybrid control board using multi-communication is designed with a low power 8-bit microcontroller, ATxmega128A1. The microcontroller consists of 8 UART (Universal asynchronous receiver/transmitter) ports, 2 kbytes EEPROM, 128 kbytes flash memory, 8 kbytes SRAM. The 8 URAT ports are used for a multi-communication modem, a GPS module, etc. The EEPROM is used for saving a configuration for running programs, and the flash memory of 128 kbytes is used for storing a F/W (Firm Ware), and the 8 kbytes SRAM is used for stack and for storing memory of global variables while running programs. If we use the multi-communication of CDMA, TRS and RF to remotely control Aid to Navigation, it is able to remove the communication shadow area. Even though there is a shadow area for an individual communication method, we can select an optimal communication method. The compatibility of data has been enhanced as using of same data frame per communication device. For the test, 8640 of data have been collected from each buoy during 30 days in every 5 minutes and the receiving rate of the data has shown more than 85 %.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.5
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• pp.35-42
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• 2008

In this paper, we propose a fast coeff_token decoding method based on the re-constructed VLCT. Since the conventional decoding method is still based on large memory accesses, it is not suitable for the multimedia services such as PMP, PMB, DVH-H where fast decoding and low power consumption are required. Based on the analysis for the codeword structure, new structure of the codeword and the corresponding memory architecture are developed in this paper. The simulation results show that the proposed algorithm achieves memory access saving from 10% to 57%, compared to the conventional decoding method. This meant that the issues of tow power consumption and high speed decoding can be resolved without video-quality and coding efficiency degradation.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.414-416
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• 2003

As environmental conditions for memory products are increasingly high speed/high density, adopting diverse system configuration, it's more and more difficult for current component tester to adopt the actual condition of field application. If system test screening is realized in component level, test coverage failure can be made more secured in the initial stage, evaluation cost can be reduced and the effectiveness of investment for the facility can be maximized. Based on the above background, component automatic system tester was developed and showed off satisfactory results per each memory device family. In this paper, component quality stabilization strategy and cost saving for tester investment through future Quality monitoring and application to mass production will be presented.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1922-1931
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• 1999

A multicast traffic’s feature is the function of providing a point to multipoints cell transmission, which is emerging from the main function of ATM switch. However, when a conventional point-to-point switch executes a multicast function, the excess load is occurred because unicast cell as well as multicast cell passed the copy network. Additionally, due to the excess load, multicast cells collide with other cells in a switch. Thus a deadlock that losses cells raises, extremely diminishes the performance of switch. An input queued switch also has a defect of the HOL (Head of Line) blocking that less lessens the performance of the switch. In the proposed multicast switch, we use shared memory switch to reduce HOL blocking and deadlock. In order to decrease switch’s complexity and cell's processing time, to improve a throughput, we utilize the method that routes a cell on a separated paths by traffic pattern and the scheduling algorithm that processes a maximum 2N cell at once in the control part. Besides, when cells is congested at an output port, a cell loss probability increases. Thus we use the Output Memory (OM) to reduce the cell loss probability. And we make use of the method that stores the assigned memory (UM, MM) with a cell by a traffic pattern and clears the cell of the Output memory after a fixed saving time to improve the memory utilization rate. The performance of the proposed switch is executed and compared with the conventional policy under the burst traffic condition through both the analysis based on Markov chain and simulation.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1003-1006
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• 2005

Vertex shader of GPU in personal computer is advanced in functions as to be half of traditional fixed T&L functions. And, capacity of memory for saving resources to process instructions is unlimited. GPU that can be programmed by programmer is needed for mobile system as well as personal computer. In this paper, we implement software virtual machine for vertex shader using C++ Language. Our goal is designing hardware GPU that can apply to mobile system. The virtual machine consists of nVidia GPU instructions. Input Data to virtual machine is generated by Microsoft fxc compiler. That is to say, Input Data is compiled shader program written in HLSL, Cg, or ASM. The virtual machine will be a reference model for designing hardware GPU and can be used for Testbed to test added or modified instruction.