• Title/Summary/Keyword: Memory Module

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A Thin Film Transistor LCD Module with Novel OverDriving Timing Controller

  • Yu, Hong-Tien;Huang, Juin-Ying;Tseng, Wen-Tse;Wen, Harchson
    • 한국정보디스플레이학회:학술대회논문집
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    • 2004.08a
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    • pp.1053-1056
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    • 2004
  • Chunghwa Picture Tubes, LTD. (CPT) has developed a Novel TFT-LCD Driving Techniquel. This new technique is developed in combination with other state-of-the-art image processing solutions such as image compression / decompression, motion detection, and noise reduction. By applying the Novel Driving Technique to the high resolution TFT-LCD, it was found that the response time can be effectively reduced with a lower overall system cost by smaller frame memory requirement, lower EMI by less memory band-width. Likewise, higher display quality can also be achieved in that the unexpected noises generated by over-drive can be eliminated. The Novel TFT-LCD Driving Technique has been successfully implemented to the 30 inch WXGA (1280${\times}$768) resolution TFT LCD commercial TV module. It was found that the quality of moving picture was better improved compared with that of the conventional fast response driving method.

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A Study on Analysis of Error Correction Code in Server System (서버 시스템 내의 오류 정정 코드 분석에 관한 연구)

  • Lee, Chang-Hwa
    • Journal of the Korea Institute of Military Science and Technology
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    • v.8 no.3 s.22
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    • pp.42-50
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    • 2005
  • In this paper, a novel method is proposed how the ECC(Error Correction Code) in server system can be investigated and the robustness of each system against noisy environment and element failure in memory module has been verified. Chipset manufacturers have hided the algorithm of their Hamming code and the user has difficulty in verification of the robustness of each system. The proposed method is very simple, but the outputs of the experiment explain the core ability of error correction in server system and helps the detection of the failure element. On the basis of these results, we could expect the robustness of digitalized weapon system and the efficient design of our own error correction code.

Development of a Detect-and-Acquisition System for Broadband Lightning Signals (광대역 낙뢰신호 탐지 및 획득 시스템 개발)

  • Song, Seung-Hun;Kim, Dong-Hyouc;Lee, Sung-Ho;Woo, Jung-Wook;Sung, Tae-Kyung
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.8
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    • pp.1503-1510
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    • 2007
  • To implement a high-precision lightning tracking system utilizing TDOA measurements, high-speed data acquisition and precise timing synchronization between ground sensors should be achieved. At the same time, considering the size of digitizer's memory, the data memory needs to be managed so that only the sampled data around the occurrence of stepped leader pulse is stored. This paper presents a detection-and-acquisition system for lightning signals that is the main equipment of ground sensor in lightning tracking system. GPS clock module is used to get precise timing synchronization and the 500MHz high speed digitizer is employed. In order to detect the leading edge of the lightning pulse and save the sampled data and its timing, lightning detection module is implemented and multi-record method is employed in the proposed system. Field experiment results show that the proposed system can detect and save the lightning signal efficiently.

Development of Portable Conversation-Type English Leaner (대화식 휴대용 영어학습기 개발)

  • Yoo, Jae-Tack;Yoon, Tae-Seob
    • Proceedings of the KIEE Conference
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    • 2004.05a
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    • pp.147-149
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    • 2004
  • Although most of the people have studied English for a long time, their English conversation capability is low. When we provide them portable conversational-type English learners by the application of computer and information process technology, such portable learners can be used to enhance their English conversation capability by their conventional conversation exercises. The core technology to develop such learner is the development of a voice recognition and synthesis module under an embedded environment. This paper deals with voice recognition and synthesis, prototype of the learner module using a DSP(Digital Signal Processing) chip for voice processing, voice playback function, flash memory file system, PC download function using USB ports, English conversation text function by the use of SMC(Smart Media Card) flash memory, LCD display function, MP3 music listening function, etc. Application areas of the prototype equipped with such various functions are vast, i.e. portable language learners, amusement devices, kids toy, control by voice, security by the use of voice, etc.

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A Study on the Dynamic Characteristics of Robot Hand based on Segmented Control (구간분할 제어를 이용한 로봇핸드의 동특성에 관한 연구)

  • Jeong S.H.;Kim H.U.;Choi S.B.;Kim G.H.;Park J.H.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2005.10a
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    • pp.310-313
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    • 2005
  • In recent years, as the robot technology is developed, the researches on the artificial muscle actuator that enable robot to move dexterously like biological organ become active. The widely used materials for artificial muscle are the shape memory alloy and the electro-active polymer. These actuators have the higher energy density than the electro-mechanical actuator such as motor. However, there are some drawbacks for actuator. SMA has the hysterical dynamic characteristics. In this paper, the simulation of anthropomophic robotic hand is performed using ADAMS and the segmented binary control for reducing the hysteresis of SMA is proposed. SMA is controlled by thermo-electric module. The relations between the force and the hysteresis are developed to verify the validity of the suggested method.

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The design of high profile H.264 intra frame encoder (H.264 하이프로파일 인트라 프레임 부호화기 설계)

  • Suh, Ki-Bum
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.11
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    • pp.2285-2291
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    • 2011
  • In this paper, H.264 high profile intra frame encoder, which integrates intra prediction, context-based adaptive variable length coding(CAVLC), and DDR2 memory control module, is proposed. The designed encoder can be operated in 440 cycle for one-macroblock. In order to verify the encoder function, we developed the reference C from JM 13.2 and verified the developed hardware using test vector generated by reference C. The designed encoder is verified in the FPGA (field programmable gate array) with operating frequency of 200 MHz for DMA (direct memory access), operating frequency of 50 MHz of Encoder module, and 25 MHz for VIM(video input module). The number of LUT is 43099, which is about 20 % of Virtex 5 XC5VLX330.

An efficient metaheuristic for multi-level reliability optimization problem in electronic systems of the ship

  • Jang, Kil-Woong;Kim, Jae-Hwan
    • Journal of Advanced Marine Engineering and Technology
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    • v.38 no.8
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    • pp.1004-1009
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    • 2014
  • The redundancy allocation problem has usually considered only the component redundancy at the lowest-level for the enhancement of system reliability. A system can be functionally decomposed into system, module, and component levels. Modular redundancy can be more effective than component redundancy at the lowest-level because in modular systems, duplicating a module composed of several components can be easier, and requires less time and skill. We consider a multi-level redundancy allocation problem in which all cases of redundancy for system, module, and component levels are considered. A tabu search of memory-based mechanisms that balances intensification with diversification via the short-term and long-term memory is proposed for its solution. To the best of our knowledge, this is the first attempt to use a tabu search for this problem. Our tabu search algorithm is compared with the previous genetic algorithm for the problem on the new composed test problems as well as the benchmark problems from the literature. Computational results show that the proposed method outstandingly outperforms the genetic algorithm for almost all test problems.

A Study of Dynamic Characteristics of Segmented Shape Memory Alloy Wire (구간 분할된 형상기억합금 와이어의 동특성에 관한 연구)

  • Jeong S.H.;Kim J.H.;Kim G.H.;Lee S.H.;Shin S.M.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2006.05a
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    • pp.329-330
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    • 2006
  • The research and development of an actuator are accelerating in the robotics industry. The electricity polymer and SMA actuator are designed simply and are produced a lot of forces per unit volume. Their motions are similar to human's motion, But the repeatability of the electricity polymer actuator is lower. The reaction velocity of the SMA actuator is slow and the travel is short. In this paper, the dynamic characteristic of the segmented SMA is studied. The SMA wire is divided by using the Thermo-electric module(TEM) to control each of segments independently. The MOSFET circuit is used to supply constant currents fer the Thermo-electric module(TEM). The hysteresis and displacement of the SMA wire according to load are measured.

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Development of Network Event Audit Module Using Data Mining (데이터 마이닝을 통한 네트워크 이벤트 감사 모듈 개발)

  • Han, Seak-Jae;Soh, Woo-Young
    • Convergence Security Journal
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    • v.5 no.2
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    • pp.1-8
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    • 2005
  • Network event analysis gives useful information on the network status that helps protect attacks. It involves finding sets of frequently used packet information such as IP addresses and requires real-time processing by its nature. Apriori algorithm used for data mining can be applied to find frequent item sets, but is not suitable for analyzing network events on real-time due to the high usage of CPU and memory and thus low processing speed. This paper develops a network event audit module by applying association rules to network events using a new algorithm instead of Apriori algorithm. Test results show that the application of the new algorithm gives drastically low usage of both CPU and memory for network event analysis compared with existing Apriori algorithm.

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SI Analysis for Quality Assurance of High-Speed Signal Interfaced Between Processor and DDR2 Memory on PCB Module (PCB Module에서의 Processor와 DDR2 메모리 사이에 인터페이스되는 고속신호 품질확보를 위한 SI해석)

  • Ha, Hyeon-Su;Kim, Min-Sung;Ha, Pan-Bong;Kim, Young-Hee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.386-389
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    • 2013
  • In this paper, for signal integrity analysing high-speed signal between a processor and a DDR2 memory, transient analysis is done and eye diagrams are generated using IBIS models of IC chips and S-parameters of transmission line. From the eye diagrams of such high-speed signals as DQ, DQS/DQSb, Clock, Address and Control, signal quality is assured through measuring timing and voltage margins during setup and hold times and verifying that the over-/under-shoot and the cross points of differential signals satisfy their specifications.

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