• 제목/요약/키워드: Memory Modeling

검색결과 309건 처리시간 0.026초

GaN Doherty 증폭기의 메모리 효과 보상을 통한 성능개선 (The Improvement of GaN Doherty Amplifier with Memory Effect Compensation)

  • 이석희;조갑제;방성일
    • 대한전자공학회논문지TC
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    • 제49권1호
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    • pp.47-52
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    • 2012
  • 전력증폭기는 기지국의 효율을 결정하는 중요한 요소이며, 효율성 제고를 위하여 GaN증폭소자를 사용한 Doherty 전력증폭기 구조에 대한 연구가 지속되고 있다. Doherty 전력증폭기의 메모리 효과는 선형성과 효율특성과 연관된 동작특성에 큰 영향을 미친다. 본 논문에서는 GaN Doherty 전력증폭기의 전열적인 비선형성 모델링과 전열적 메모리 효과가 GaN Doherty 증폭기의 왜곡형성과 보상에 대하여 연구하였다. GaN Doherty 증폭기의 전열적 메모리 특성을 모델링하기 위하여 순시적으로 소모되는 전력과 순시 접합온도의 정확한 관계식을 정립하였다. 제안된 모델의 파라미터로부터 GaN Doherty 전력증폭기의 비선형왜곡과 전열적 메모리 효과를 보상할 수 있는 전치왜곡선형화기 모델을 설계하였다. 제안된 모델의 성능평가는 37dBm GaN Doherty 전력증폭기와 ADS Tool을 사용하여 왜곡특성 성능개선정도를 검증하였다. 선형화된 GaN 전력증폭기의 2-tone 출력스펙트럼에서 약 16 dB의 왜곡개선효과를 보였다.

고속 스토리지 환경의 메모리 관리를 위한 TLB 미스율 및 페이지 폴트율 모델링 (Modeling of TLB Miss Rate and Page Fault Rate for Memory Management in Fast Storage Environments)

  • 박윤주;반효경
    • 한국인터넷방송통신학회논문지
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    • 제22권1호
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    • pp.65-70
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    • 2022
  • 최근 고속 스토리지의 활성화로 인해 하드디스크를 전제로 설계된 메모리 관리 시스템에 대한 재고가 필요한 시점에 이르렀다. 본 논문은 고속 스토리지 환경에서 메모리 접근 시간이 페이지 크기에 민감한 점을 관찰하고, 그 이유가 페이지 폴트율보다 TLB 미스율이 메모리 접근시간에 미치는 영향력이 커졌기 때문임을 확인하였다. 또한, TLB 미스율과 페이지 폴트율이 페이지 크기 변화에 따라 상충관계를 나타냄을 확인하고 이를 모델링하는 함수를 설계하였다. TLB 미스율의 경우 파워 피팅을 통한 모델링을 하였으며, 페이지 폴트율의 경우 2개의 항을 가진 지수 피팅을 통한 모델링을 하였다. 검증 실험을 통해 설계된 모델 함수에 의한 예측치가 실제 결과값을 잘 반영함을 확인하였다.

원자단위 Electromechanical 모델링을 통한 나노튜브 메모리 연구 (An Atomistic Modeling for Electromechanical Nanotube Memory Study)

  • 이강환;권오근
    • 한국전기전자재료학회논문지
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    • 제19권2호
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    • pp.116-125
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    • 2006
  • We have presented a nanoelectromechanical (NEM) model based on atomistic simulations. Our models were applied to a NEM device as called a nanotube random access memory (NRAM) operated by an atomistic capacitive model including a tunneling current model. We have performed both static and dynamic analyses of a NRAM device. The turn-on voltage obtained from molecular dynamics simulations was less than the half of the turn-on voltage obtained from the static simulation. Since the suspended carbon nanotube (CNT) oscillated with the amplitude for the oscillation center under an externally applied force, the quantity of the CNT-gold interaction in the static analysis was different from that in the dynamic analysis. When the gate bias was applied, the oscillation centers obtained from the static analysis were different from those obtained from the dynamics analysis. Therefore, for the range of the potential difference that the CNT-gold interaction effects in the static analysis were negligible, the vibrations of the CNT in the dynamics analysis significantly affected the CNT-gold interaction energy and the turn-on voltage. The turn-on voltage and the tunneling resistance obtained from our tunneling current model were in good agreement with previous experimental and theoretical works.

Use of copper shape memory alloys in retrofitting historical monuments

  • El-Borgi, S.;Neifar, M.;Jabeur, M. Ben;Cherif, D.;Smaoui, H.
    • Smart Structures and Systems
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    • 제4권2호
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    • pp.247-259
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    • 2008
  • The potential use of Cu-based shape memory alloys (SMA) in retrofitting historical monuments is investigated in this paper. This study is part of the ongoing work conducted in Tunisia within the framework of the FP6 European Union project (WIND-CHIME) on the use of appropriate modern seismic protective systems in the conservation of Mediterranean historical buildings in earthquake-prone areas. The present investigation consists of a finite element simulation, as a preliminary to an experimental study where a cantilever masonry wall, representing a part of a historical monument, is subjected to monotonic and quasi-static cyclic loadings around a horizontal axis at the base level. The wall was retrofitted with an array of copper SMA wires with different cross-sectional areas. A new model is proposed for heat-treated copper SMAs and is validated based on published experimental results. A series of nonlinear finite element analyses are then performed on the wall for the purpose of assessing the SMA device retrofitting capabilities. Simulation results show an improvement of the wall response for the case of monotonic and quasi-static cyclic loadings.

RFI에 기인한 안테나 성능 저하 분석 (Analysis of Performance Degradation of Antenna due to Radio Frequency Interference)

  • 이호상;김광호;윤진성;이대희;황찬석;나완수
    • 전기학회논문지
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    • 제66권4호
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    • pp.651-658
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    • 2017
  • This paper proposes an analysis method of performance degradation of antenna due to radio frequency interference between an antenna and adjacent noise sources using active scattering parameters. The radio frequency interference can be analyzed by the measured or simulated scattering parameters and by excited noise sources in the circuit as well. In this paper, a planar inverted-F antenna and a noise source are designed and fabricated to analyze radio frequency interference between the planar inverted-F antenna and noise source. The proposed analysis method uses active scattering parameters, of which verification is experimentally verified, and in simulation as well.

DFP Method 기반의 새로운 적응형 디지털 전치 왜곡 선형화기 알고리즘 개발 (A Design of New Digital Adaptive Predistortion Linearizer Algorithm Based on DFP(Davidon-Fletcher-Powell) Method)

  • 장정석;최용규;서경환;홍의석
    • 한국전자파학회논문지
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    • 제22권3호
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    • pp.312-319
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    • 2011
  • 본 논문에서는 디지털 전치 왜곡 선형화기를 위한 새로운 선형화 알고리즘을 제안하였다. 제안된 알고리즘은 DFP(Davidon-Fletcher-Powell) method를 활용하였다. 또한, 기존의 알고리즘보다 빠른 수렴 속도를 가지며, 가중치 갱신 step-size를 초기 설정값 없이 매 루틴마다 최적의 값을 갱신한다. 전력증폭기 모델링에는 전력 증폭기의 기억 효과를 모델링할 수 있는 memory polynomial 모델을 사용하였고, 선형화기의 전체적인 구성은 간접 학습 구조를 따랐다. 제안된 알고리즘의 성능 검증을 위해 기존의 LMS(Least Mean-Squares), RLS(Recursive Least squares) 알고리즘과 비교하였다.

차세대 비휘발성 메모리에 사용되는 High-k 절연막의 터널링 특성 (Tunneling Properties in High-k Insulators with Engineered Tunnel Barrier for Nonvolatile Memory)

  • 오세만;정명호;박군호;김관수;정홍배;이영희;조원주
    • 한국전기전자재료학회논문지
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    • 제22권6호
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    • pp.466-468
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    • 2009
  • The metal-insulator-silicon (MIS) capacitors with $SiO_2$ and high-k dielectrics ($HfO_2$, $Al_2O_3$) were fabricated, and the current-voltage characteristics were investigated. Especially, an effective barrier height between metal gate and dielectric was extracted by using Fowler-Nordheim (FN) plot and Direct Tunneling (DT) plot of quantum mechanical(QM) modeling. The calculated barrier heights of thermal $SiO_2$, ALD $SiO_2$, $HfO_2$ and $Al_2O_3$ are 3.35 eV, 0.6 eV, 1.75 eV, and 2.65 eV, respectively. Therefore, the performance of non-volatile memory devices can be improved by using engineered tunnel barrier which is considered effective barrier height of high-k materials.

DR-LSTM: Dimension reduction based deep learning approach to predict stock price

  • Ah-ram Lee;Jae Youn Ahn;Ji Eun Choi;Kyongwon Kim
    • Communications for Statistical Applications and Methods
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    • 제31권2호
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    • pp.213-234
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    • 2024
  • In recent decades, increasing research attention has been directed toward predicting the price of stocks in financial markets using deep learning methods. For instance, recurrent neural network (RNN) is known to be competitive for datasets with time-series data. Long short term memory (LSTM) further improves RNN by providing an alternative approach to the gradient loss problem. LSTM has its own advantage in predictive accuracy by retaining memory for a longer time. In this paper, we combine both supervised and unsupervised dimension reduction methods with LSTM to enhance the forecasting performance and refer to this as a dimension reduction based LSTM (DR-LSTM) approach. For a supervised dimension reduction method, we use methods such as sliced inverse regression (SIR), sparse SIR, and kernel SIR. Furthermore, principal component analysis (PCA), sparse PCA, and kernel PCA are used as unsupervised dimension reduction methods. Using datasets of real stock market index (S&P 500, STOXX Europe 600, and KOSPI), we present a comparative study on predictive accuracy between six DR-LSTM methods and time series modeling.

임베디드 SoC를 위한 Bus-splitting 기법 적용 ECC 보안 프로세서의 구현 (An Implementation of ECC(Elliptic Curve Cryptographic)Processor with Bus-splitting method for Embedded SoC(System on a Chip))

  • 최선준;장우영;김영철
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2005년도 추계종합학술대회
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    • pp.651-654
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    • 2005
  • In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

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Numerical Analysis of SMA Hybrid Composite Plate Subjected to Low-Velocity Impact

  • Kim, Eun-Ho;Roh, Jin-Ho;Lee, In
    • International Journal of Aeronautical and Space Sciences
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    • 제8권2호
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    • pp.76-81
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    • 2007
  • The fiber reinforced laminated composite structures are very susceptible to be damaged when they are impacted by foreign objects. To increase the impact resistance of the laminated composite structures, shape memory alloy(SMA) thin film is embedded in the structure. For the numerical impact analysis of SMA hybrid composite structures, SMA modeling tool is developed to consider pseudoelastic effect of SMAs. Moreover, the damage analysis is considered using failure criteria and a simple damage model for reasonable impact analysis. The numerical results are verified with the experimental ones. Impact analyses for composite plate with pre-strained SMAs are numerically performed and the damage areas are investigated.