• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.266-269
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• 2012

High-efficiency built-in redundancy analysis (BIRA) is presented. The proposed BIRA uses three techniques to achieve a high repair rate using spare mapping registers with adjustable fault tags to reduce area overhead. Simulation results show that the proposed BIRA is a reasonable solution for embedded memories.

• ETRI Journal
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• v.31 no.3
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• pp.339-341
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• 2009

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.230-235
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• 1992

We propose a method of generating data to train a neural network controller. The data can be prepared directly by an iterative learning technique which repeatedly adjusts the control input to improve the tracking quality of the desired trajectory. Instead of storing control input data in memory as in iterative learning control, the neural network stores the mapping between the control input and the desired output. We apply this concept to the trajectory control of a two link robot manipulator with a feedforward neural network controller and a feedback linear controller. Simulation results show good generalization of the neural network controller.

• Korean Journal of Microbiology
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• v.24 no.1
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• pp.12-17
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• 1986

A new computer algorithm is described to order the restriction fragments of plasmid DNA which has been cleaved with several restriction endonucleases in single or double digestions rapidly with realistic error rates. The permutation and high weight on small fragments methods construct all logical circular map solutions. The program is written in Apple BASIC and run on an Apple II plus microcomputer with 64K memory. Several examples are presented which indicate the high efficiency of the profram in construction possible restriction map for YEp24.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.101-121
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• 2010

This paper presents an intelligent prefetching technique that significantly improves performance of hybrid fash-disk storage, a combination of flash memory and hard disk. Since flash memory embedded in a hybrid device is much faster than hard disk in terms of I/O operations, it can be utilized as a 'cache' space to improve system performance. The basic strategy for prefetching is to utilize sequential pattern mining, with which we can extract the access patterns of objects from historical access sequences. We use two techniques for enhancing the performance of hybrid storage with prefetching. One of them is to modify a FAST algorithm for mapping the flash memory. The other is to extend the unit of prefetching to a block level as well as a file level for effectively utilizing flash memory space. For evaluating the proposed technique, we perform the experiments using the synthetic data and real UCC data, and prove the usability of our technique.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.8
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• pp.1605-1614
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• 2009

The technique of simultaneous localization and mapping is the most important research topic in mobile robotics. In the process of building a map in its available memory, the robot memorizes environmental information on the plane of grid or topology. Several approaches about this technique have been presented so far, but most of them use mapping technique as either grid-based map or topology-based map. In this paper we propose a frame of solving the SLAM problem of linking map covering, map building, localizing, path finding and obstacle avoiding in an automatic way. Some algorithms integrating grid and topology map are considered and this make the SLAM performance faster and more stable. The proposed scheme uses an occupancy grid map in representing the environment and then formulate topological information in path finding by A${\ast}$ algorithm. The mapping process is shown and the shortest path is decided on grid based map. Then topological information such as direction, distance is calculated on simulator program then transmitted to robot hardware devices. The localization process and the dynamic obstacle avoidance can be accomplished by topological information on grid map. While mapping and moving, pose of the robot is adjusted for correct localization by implementing additional pixel based image layer and tracking some features. A laser range finer and electronic compass systems are implemented on the mobile robot and DC geared motor wheels are individually controlled by the adaptive PD control method. Simulations and experimental results show its performance and efficiency of the proposed scheme are increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.58-64
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• 2009

For the success of the reconfigurable computing, the algorithm for mapping operations onto coarse-grained reconfigurable architecture is very important. This paper proposes a resource-aware mapping system for the coarse-grained reconfigurable architecture and its own underlying heuristic algorithm. The operation assignment and the routing path allocation are simultaneously performed with a cycle-accurate time-exclusive resource model. The proposed algorithm minimizes the communication resource usage and the global memory access with the list scheduling heuristic. The operation to be mapped are prioritized with general properties of data flow. The evaluations of the proposed algorithm show that the performance is significantly enhanced in several benchmark applications.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.57-64
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• 2007

This paper proposed the low power texture cache for mobile 3D graphics accelerators. It is very important to reduce the leakage power in the standby mode for mobile 3D graphics accelerators and the memory access latency of texture mapping in the active mode which needs a large memory bandwidth. The proposed structure reduces the leakage power using variable threshold values of power mode transitions according to the selected texture filtering algorithms of application programs, which has the run time gain for texture mapping. In the trace driven cache simulation the proposed structure shows the best 7% performance gain to the previous MSA cache according to the new performance metric considering both normalized leakage power and run time impact.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.5
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• pp.1139-1144
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• 2008

In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform $100x{\tims}1000x$ faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform

• Proceedings of the National Institute of Ecology of the Republic of Korea
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• v.4 no.4
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• pp.159-176
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• 2023

The conservation of the raccoon dog (Nyctereutes procyonoides) in South Korea requires the protection and preservation of natural habitats while additionally ensuring coexistence with human activities. Applying habitat map modeling techniques provides information regarding the distributional patterns of raccoon dogs and assists in the development of future conservation strategies. The purpose of this study is to generate potential habitat distribution maps for the raccoon dog in South Korea using geospatial technology-based models. These models include the frequency ratio (FR) as a bivariate statistical approach, the group method of data handling (GMDH) as a machine learning algorithm, and convolutional neural network (CNN) and long short-term memory (LSTM) as deep learning algorithms. Moreover, the imperialist competitive algorithm (ICA) is used to fine-tune the hyperparameters of the machine learning and deep learning models. Moreover, there are 14 habitat characteristics used for developing the models: elevation, slope, valley depth, topographic wetness index, terrain roughness index, slope height, surface area, slope length and steepness factor (LS factor), normalized difference vegetation index, normalized difference water index, distance to drainage, distance to roads, drainage density, and morphometric features. The accuracy of prediction is evaluated using the area under the receiver operating characteristic curve. The results indicate comparable performances of all models. However, the CNN demonstrates superior capacity for prediction, achieving accuracies of 76.3% and 75.7% for the training and validation processes, respectively. The maps of potential habitat distribution are generated for five different levels of potentiality: very low, low, moderate, high, and very high.