• Title/Summary/Keyword: Memory Information

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Design and Evaluation of a NIC-Driven Host-Independent Network System (네트워크 인터페이스 카드에 기반한 호스트 독립적인 네트워크 시스템의 설계 및 성능평가)

  • Yim Keun Soo;Cha Hojung;Koh Kern
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.11
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    • pp.626-634
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    • 2004
  • In a client-server model, network server systems suffer from both heavy communication and computational loads. While communication channels become increasingly speedy, the existing protocol stack architectures still include mainly three performance bottlenecks of protocol stack processing, system call, and network interrupt overheads. To address these obstacles, in this paper we present a host-independent network system where a network interface card (NIC) is utilized in an efficient manner. First, by offloading network-related portion to the NIC, the host can fully utilize its processing power for other useful purposes. Second, it eliminates the system call overhead, such as context-switching and memory copy operations, since the host communicates with the NIC through its user-level libraries. Third, it a] so reduces the network interrupt operation count as the host handles the interrupt in a segment instead of a packet. The experimental results show that the proposed network system reduces the host CPU overhead for communication system by 68-71%. It also shows that the proposed system improves the communication speed by 11-83% under heavy computational and communication load conditions.

Building a Log Framework for Personalization Based on a Java Open Source (JAVA 오픈소스 기반의 개인화를 지원하는 Log Framework 구축)

  • Sin, Choongsub;Park, Seog
    • KIISE Transactions on Computing Practices
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    • v.21 no.8
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    • pp.524-530
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    • 2015
  • A log is for text monitoring and perceiving the issues of a system during the development and operation of a program. Based on the log, system developers and operators can trace the cause of an issue. In the development phase, it is relatively simple for a log to be traced while there are only a small number of personnel uses of a system such as developers and testers. However, it is the difficult to trace a log when many people can use the system in the operation phase. In major cases, because a log cannot be tracked, even tracing is dropped. This study proposed a simplified tracing of a log during the system operation. Thus, the purpose is to create a log on the run time based on an ID/IP, using features provided by the Logback. It saves an ID/IP of the tracking user on a DB, and loads the user's ID/IP onto the memory to trace once WAS starts running. Before the online service operates, an Interceptor is executed to decide whether to load a log file, and then it generates the service requested by a certain user in a separate log file. The load is insignificant since the arithmetic operation occurs in a JVM, although every service must pass through the Interceptor to be executed.

Extension of Wright-based Connector Considering Efficiency Characteristics of Component (컴포넌트 효율성 특성을 고려한 Wright기반의 커넥터 확장)

  • 정화영;송영재
    • Journal of KIISE:Software and Applications
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    • v.30 no.12
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    • pp.1185-1192
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    • 2003
  • In the component assembly and composition technique of software architecture, It is operated that the existing composition techniques based on architecture, ACME, Wright etc., used in FIFO with the direct connection structure between components through connector's Role. But, when the non-synchronizing request of components that have different characteristics occurs, the FIFO techniques is applied to the connector is difficult to process and operate effectively because of the high performance component waiting the sequence order if the low performance component is allocated first. Thus, the allocated request process according to the priority considering the characteristics of each call components in connector is necessary to improve the operation of assembled component. In this research, we extend the connector part that is available in multiplex connection structure based on existent Wright specification. For service process requested from component, the connector part is designed and implemented to operating with priority sequence through calculating the weight of CPU use rate, bean requesting process time and memory use rate among the efficiency elements of assembled components. To verify the efficiency if this designed connector, we implemented 20 samples EJB components that have different efficiency characteristics and applied these samples components to designed connector. The operating results with this designed connector show that the efficient operation of whole system is possible though the processing time takes 481ms more than the time of the existing FIFO techniques.

Data Cache System based on the Selective Bank Algorithm for Embedded System (내장형 시스템을 위한 선택적 뱅크 알고리즘을 이용한 데이터 캐쉬 시스템)

  • Jung, Bo-Sung;Lee, Jung-Hoon
    • The KIPS Transactions:PartA
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    • v.16A no.2
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    • pp.69-78
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    • 2009
  • One of the most effective way to improve cache performance is to exploit both temporal and spatial locality given by any program executive characteristics. In this paper we present a high performance and low power cache structure with a bank selection mechanism that enhances exploitation of spatial and temporal locality. The proposed cache system consists of two parts, i.e., a main direct-mapped cache with a small block size and a fully associative buffer with a large block size as a multiple of the small block size. Especially, the main direct-mapped cache is constructed as two banks for low power consumption and stores a small block which is selected from fully associative buffer by the proposed bank selection algorithm. By using the bank selection algorithm and three state bits, We selectively extend the lifetime of those small blocks with high temporal locality by storing them in the main direct-mapped caches. This approach effectively reduces conflict misses and cache pollution at the same time. According to the simulation results, the average miss ratio, compared with the Victim and STAS caches with the same size, is improved by about 23% and 32% for Mibench applications respectively. The average memory access time is reduced by about 14% and 18% compared with the he victim and STAS caches respectively. It is also shown that energy consumption of the proposed cache is around 10% lower than other cache systems that we examine.

An Efficient WLAN Device Power Control Technique for Streaming Multimedia Contents over Mobile IP Storage (모바일 IP 스토리지 상에서 멀티미디어 컨텐츠 실행을 위한 효율적인 무선랜 장치 전력제어 기법)

  • Nam, Young-Jin;Choi, Min-Seok
    • The KIPS Transactions:PartA
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    • v.16A no.5
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    • pp.357-368
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    • 2009
  • Mobile IP storage has been proposed to overcome storage limitation in the flash memory and hard disks. It provides almost capacity-free space for mobile devices over wireless IP networks. However, battery lifetime of the mobile devices is reduced rapidly because of power consumption with continuous use of a WLAN device when multimedia contents are being streamed through the mobile IP storage. This paper proposes an energy-efficient WLAN device power control technique for streaming multimedia contents with the mobile IP storage. The proposed technique consists of a prefetch buffer input/output module, a WLAN device power control module, and a reconfigurable prefetch buffer module. Besides, it adaptively determines the size of the prefetch buffer according to a quality of the multimedia contents, and it dynamically controls the power mode of the WLAN device on the basis of power on-off operations while streaming the multimedia contents. We evaluate the performance of the proposed technique on a PXA270-based mobile device that employs the embedded linux 2.6.11, Intel iSCSI reference codes, and a WLAN device. Extensive experiments reveal that the proposed technique can save the energy consumption of the WLAN device up to 8.5 times with QVGA multimedia contents, as compared with no power control.

A Performance Improvement of Linux TCP/IP Stack based on Flow-Level Parallelism in a Multi-Core System (멀티코어 시스템에서 흐름 수준 병렬처리에 기반한 리눅스 TCP/IP 스택의 성능 개선)

  • Kwon, Hui-Ung;Jung, Hyung-Jin;Kwak, Hu-Keun;Kim, Young-Jong;Chung, Kyu-Sik
    • The KIPS Transactions:PartA
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    • v.16A no.2
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    • pp.113-124
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    • 2009
  • With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.

Implementation of User-friendly Intelligent Space for Ubiquitous Computing (유비쿼터스 컴퓨팅을 위한 사용자 친화적 지능형 공간 구현)

  • Choi, Jong-Moo;Baek, Chang-Woo;Koo, Ja-Kyoung;Choi, Yong-Suk;Cho, Seong-Je
    • The KIPS Transactions:PartD
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    • v.11D no.2
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    • pp.443-452
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    • 2004
  • The paper presents an intelligent space management system for ubiquitous computing. The system is basically a home/office automation system that could control light, electronic key, and home appliances such as TV and audio. On top of these basic capabilities, there are four elegant features in the system. First, we can access the system using either a cellular Phone or using a browser on the PC connected to the Internet, so that we control the system at any time and any place. Second, to provide more human-oriented interface, we integrate voice recognition functionalities into the system. Third, the system supports not only reactive services but also proactive services, based on the regularities of user behavior. Finally, by exploiting embedded technologies, the system could be run on the hardware that has less-processing power and storage. We have implemented the system on the embedded board consisting of StrongARM CPU with 205MHz, 32MB SDRAM, 16MB NOR-type flash memory, and Relay box. Under these hardware platforms, software components such as embedded Linux, HTK voice recognition tools, GoAhead Web Server, and GPIO driver are cooperated to support user-friendly intelligent space.

HVIA-GE: A Hardware Implementation of Virtual Interface Architecture Based On Gigabit Ethernet (HVIA-GE: 기가비트 이더넷에 기반한 Virtual Interface Architecture의 하드웨어 구현)

  • 박세진;정상화;윤인수
    • Journal of KIISE:Computer Systems and Theory
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    • v.31 no.5_6
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    • pp.371-378
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    • 2004
  • This paper presents the implementation and performance of the HVIA-GE card, which is a hardware implementation of the Virtual Interface Architecture (VIA) based on Gigabit Ethernet. The HVIA-GE card is a 32-bit/33MHz PCI adapter containing an FPGA for the VIA protocol engine and a Gigabit Ethernet chip set to construct a high performance physical network. HVIA-GE performs virtual-to-physical address translation, Doorbell, and send/receive completion operations in hardware without kernel intervention. In particular, the Address Translation Table (ATT) is stored on the local memory of the HVIA-GE card, and the VIA protocol engine efficiently controls the address translation process by directly accessing the ATT. As a result, the communication overhead during send/receive transactions is greatly reduced. Our experimental results show the maximum bandwidth of 93.7MB/s and the minimum latency of 11.9${\mu}\textrm{s}$. In terms of minimum latency HVIA-GE performs 4.8 times and 9.9 times faster than M-VIA and TCP/IP, respectively, over Gigabit Ethernet. In addition, the maximum bandwidth of HVIA-GE is 50.4% and 65% higher than M-VIA and TCP/IP respectively.

eRPL : An Enhanced RPL Based Light-Weight Routing Protocol in a IoT Capable Infra-Less Wireless Networks (사물 인터넷 기반 기기 간 통신 무선 환경에서 향상된 RPL 기반 경량화 라우팅 프로토콜)

  • Oh, Hayoung
    • KIPS Transactions on Computer and Communication Systems
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    • v.3 no.10
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    • pp.357-364
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    • 2014
  • The first mission for the IoT based hyper-connectivity communication is developing a device-to-device communication technique in infra-less low-power and lossy networks. In a low-power and lossy wireless network, IoT devices and routers cannot keep the original path toward the destination since they have the limited memory. Different from the previous light-weight routing protocols focusing on the reduction of the control messages, the proposed scheme provides the light-weight IPv6 address auto-configuration, IPv6 neighbor discovery and routing protocol in a IoT capable infra-less wireless networks with the bloom filer and enhanced rank concepts. And for the first time we evaluate our proposed scheme based on the modeling of various probability distributions in the IoT environments with the lossy wireless link. Specifically, the proposed enhanced RPL based light-weight routing protocol improves the robustness with the multi-paths locally established based on the enhanced rank concepts even though lossy wireless links are existed. We showed the improvements of the proposed scheme up to 40% than the RPL based protocol.

The Behavior Economics in Storytelling (이야기하기의 행동경제학)

  • Kim, Kyung-Seop;Kim, Jeong-Lae
    • The Journal of the Convergence on Culture Technology
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    • v.5 no.4
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    • pp.329-337
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    • 2019
  • It is true that many tales delivered in an 'Story-telling' auditorium or theater have not so much exquisite and refined forms as distorted and deteriorated ones. Furthermore, when false interpretations of tale-performers added into the category of the texts of tales, the problems can be made worse. In case of oral folk tales, there can be discordance between the standpoint of a tale-performer and the contents of a tale. This thesis is directly aimed at pointing out the 'Behavior Economics' problems concerned with the reading and interpretation of tales through investigating the missing parts of a text in reading tales. Man's rationality is meant to be confined to bounded rationality. Instead of making best choices, bounded rationality leads consumers to make a decision which they think suffices themselves to the point requiring no more consideration on the given item. It is the very Heuristic that does work in the process of this simplified decision making process. Heuristic utilizes established empirical notion and specific information, and that's why there can be cognitive 'Biases' sometimes leading to inaccurate judgment. As Oral Literature is basically based on heavy guesswork and perceptual biases of general public, it is imperative to contemplate oral literature in the framework of Heuristic of behavior economics. This thesis deals with thinking types and behavioral patterns of the general public in the perspective of heuristic by examining 'Story-tellings' on the basis of personal or public memory. In addition, heuristic involves how to deal with significant but intangible content such as the errors of oral story teller, the deviations of the story, and responses of the audience.