• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.46-54
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• 2006

Recently, the important of a personal identification is increasing according to expansion using each on-line commercial transaction and personal ID-card. Although a personal ID-card embedded RFID(Radio Frequency Identification) tag is gradually increased, the way for a person's identification is deficiency. So we need automatic methods. Because RFID tag is vary small storage capacity of memory, it needs effective feature extraction method to store personal biometrics information. We need new recognition method to compare each feature. In this paper, we studied the face verification system using Hippocampal neuron modeling algorithm which can remodel the hippocampal neuron as a principle of a man's brain in engineering, then it can learn the feature vector of the face images very fast. and construct the optimized feature each image. The system is composed of two parts mainly. One is feature extraction using NMF(Non-negative Matrix Factorization) and LDA(Linear Discriminants Analysis) mixture algorithm and the other is hippocampal neuron modeling and recognition simulation experiments confirm the each recognition rate, that are face changes, pose changes and low-level quality image. The results of experiments, we can compare a feature extraction and learning method proposed in this paper of any other methods, and we can confirm that the proposed method is superior to the existing method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.100-108
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• 2018

This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto-processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a $0.18{\mu}m$ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of $6{\times}3,072$ bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.292-294
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• 2018

Recently, damage caused by natural disasters such as fire, earthquake, heavy rains and heavy snow is increasing. In addition, traffic accidents due to freezing, fog and fire in tunnels and bridges are frequently occurring. In such a disaster situation, it is very important to take prompt action by the person in charge of managing the facility and area.To this end, a disaster broadcasting system is used, but in the existing system, the broadcasting room and the speaker are connected by a wired connection. Also, the person in charge has to be in the broadcasting room to broadcast, which has a problem of delaying the time. In this paper, we design a disaster broadcasting system using LTE modem. The designed system enables a broadcasting person to make a call to a broadcasting system from anywhere using a cellular phone and a public telephone. Broadcasting via telephone is possible only with the telephone number pre-registered in the system and can be registered / deleted by the administrator. The registered telephone number, incoming voice file, and announcement voice for automatic broadcasting are stored in the system internal SD memory for convenient management. This disaster broadcasting system is expected to contribute to quick and convenient disaster broadcasting.

• Journal of the Korea Society of Computer and Information
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• v.18 no.10
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• pp.1-12
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• 2013

This paper explores design space of many-core processors for a fire feature extraction algorithm. This paper evaluates the impact of varying the number of cores and memory sizes for the many-core processor and identifies an optimal many-core processor in terms of performance, energy efficiency, and area efficiency. In this study, we utilized 90 samples with dimensions of $256{\times}256$ (60 samples containing fire and 30 samples containing non-fire) for experiments. Experimental results using six different many-core architectures (PEs=16, 64, 256, 1,024, 4,096, and 16,384) and the feature extraction algorithm of fire indicate that the highest area efficiency and energy efficiency are achieved at PEs=1,024 and 4,096, respectively, for all fire/non-fire containing movies. In addition, all the six many-core processors satisfy the real-time requirement of 30 frames-per-second (30 fps) for the algorithm.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.19-30
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• 2013

We study sub-Peres functions that are defined recursively as Peres function for random number generation. Instead of using two parameter functions as in Peres function, the sub-Peres functions uses only one parameter function. Naturally, these functions produce less random bits, hence are not asymptotically optimal. However, the sub-Peres functions runs in linear time, i.e., in O(n) time rather than O(n logn) as in Peres's case. Moreover, the implementation is even simpler than Peres function not only because they use only one parameter function but because they are tail recursive, hence run in a simple iterative manner rather than by a recursion, eliminating the usage of stack and thus further reducing the memory requirement of Peres's method. And yet, the output rate of the sub-Peres function is more than twice as much as that of von Neumann's method which is widely known linear-time method. So, these methods can be used, instead of von Neumann's method, in an environment with limited computational resources like mobile devices. We report the analyses of the sub-Peres functions regarding their running time and the exact output rates in comparison with Peres function and other known methods for random number generation. Also, we discuss how these sub-Peres function can be implemented.

• Journal of the Korea Society of Computer and Information
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• v.15 no.8
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• pp.13-21
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• 2010

One of the most distinguished features of the DHP association rules mining algorithm is that it counts the support of hash key combinations composed of k items at phase k-1, and uses the counted support for pruning candidate large itemsets to improve performance. At this time, it is desirable for each hash key combination to have a separate count variable, where it is impossible to allocate the variables owing to memory shortage. So, the algorithm uses a direct hashing mechanism in which several hash key combinations conflict and are counted in a same hash bucket. But the direct hashing mechanism is not efficient because the distribution of hash key combinations is unvalanced by the characteristics sourced from the mining process. This paper proposes a mapped perfect hashing function which maps the region of hash key combinations into a continuous integer space for phase 3 and maximizes the efficiency of direct hashing mechanism. The results of a performance test experimented on 42 test data sets shows that the average performance improvement of the proposed hashing mechanism is 7.3% compared to the existing method, and the highest performance improvement is 16.9%. Also, it shows that the proposed method is more efficient in case the length of transactions or large itemsets are long or the number of total items is large.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.6
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• pp.9-18
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• 2005

This paper proposes the color decomposition method for multi-primary display (MPD) using a 3-dimensional look-up-table (3D-LUT) in a linearized LAB space. The proposed method decomposes conventional three-primary colors into the multi-primary control values of a display device under constraints of tristimulus match. To reproduce images on the MPD, the color signals should be estimated from a device-independent color space, such as CIEXYZ and CIELAB. In this paper, the linearized LAB space is used due to its linearity and additivity in color conversion. The proposed method constructs the 3-D LUT, which contain gamut boundary information to calculate color signals of the MPD. For the image reproduction, standard RGB or CIEXYZ is transformed to the linearized LAB and then hue and chroma are computed to refer to the 3D-LUT. In the linearlized LAB space, the color signals of a gamut boundary point with the same lightness and hue of an input point are calculated. Also, color signals of a point on gray axis are calculated with the same lightness of an input. With gamut boundary points and input point, color signals of the input points are obtained with the chroma ratio divided by the chroma of the gamut boundary point. Specially, for the hue change, neighboring boundary points are employed. As a result the proposed method guarantees the continuity of color signals and computational efficiency, and requires less amount of memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.619-630
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• 2003

We present a method of runtime configuration scheduling in reconfigurable SoC design. As a model of computation, we use a popular formal model of computation, hierarchical FSM (HFSM) with synchronous dataflow (SDF) model, in short, HFSM-SDF model. In reconfigurable SoC design with HFSM-SDF model, the problem of configuration scheduling becomes challenging due to the dynamic behavior of the system such as concurrent execution of state transitions (by AND relation), complex control flow (HFSM), and complex schedules of SDF actor firing. This makes it hard to hide configuration latency efficiently with compile-time static configuration scheduling. To resolve the problem, it is necessary to know the exact order of required configurations during runtime and to perform runtime configuration scheduling. To obtain the exact order of configurations, we exploit the inherent property of HFSM-SDF that the execution order of SDF actors can be determined before executing the state transition of top FSM. After obtaining the order information and storing it in the ready configuration queue (ready CQ), we execute the state transition. During the execution, whenever there is FPGA resource available, a new configuration is selected from the ready CQ and fetched by the runtime configuration scheduler. We applied the method to an MPEG4 decoder and IS95 design and obtained up to 21.8% improvement in system runtime with a negligible overhead of memory usage.

• Journal of the Korea Computer Graphics Society
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• v.17 no.3
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• pp.1-7
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• 2011

Recently, various researches have been proposed to accelerate GPU-based volume ray-casting. However, those researches may cause several problems such as bottleneck of data transmission between CPU and GPU, requirement of additional video memory for hierarchical structure and increase of processing time whenever opacity transfer function changes. In this paper, we propose an efficient GPU-based empty space skipping technique to solve these problems. We store maximum density in a brick of volume dataset on a vertex element. Then we delete vertices regarded as transparent one by opacity transfer function in geometry shader. Remaining vertices are used to generate bounding boxes of non-transparent area that helps the ray to traverse efficiently. Although these vertices are independent on viewing condition they need to be reproduced when opacity transfer function changes. Our technique provides fast generation of opaque vertices for interactive processing since the generation stage of the opaque vertices is running in GPU pipeline. The rendering results of our algorithm are identical to the that of general GPU ray-casting, but the performance can be up to more than 10 times faster.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06b
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• pp.238-240
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• 2006

네트워크상에서 발생하는 다양한 형태의 대량의 데이터를 정확하고 효율적으로 분석하기 위해 설계되고 있는 마이닝 시스템들은 목표지향적으로 훈련데이터들을 어떻게 구축하여 다룰 것인지에 대한 문제보다는 대부분 얼마나 많은 데이터 마이닝 기법을 지원하고 이를 적용할 수 있는지 등의 기법에 초점을 두고 있다. 따라서, 점점 더 에이전트화, 분산화, 자동화 및 은닉화 되는 최근의 보안공격기법을 정확하게 탐지하기 위한 방법은 미흡한 실정이다. 본 연구에서는 유비쿼터스 환경 내에서 발생 가능한 문제 중 복잡하고 지능화된 침입패턴의 탐지를 위해 데이터 마이닝 기법과 결함허용방법을 이용하는 개선된 학습알고리즘과 후처리 방법에 의한 RTPID(Refinement Training and Post-processing for Intrusion Detection)시스템을 제안한다. 본 논문에서의 RTPID 시스템은 active learning과 post-processing을 이용하여, 네트워크 내에서 발생 가능한 침입형태들을 정확하고 효율적으로 다루어 분석하고 있다. 이는 기법에만 초점을 맞춘 기존의 데이터마이닝 분석을 개선하고 있으며, 특히 제안된 분석 프로세스를 진행하는 동안 능동학습방법의 장점을 수용하여 학습효과는 높이며 비용을 감소시킬 수 있는 자가학습방법(self learning)방법의 효과를 기대할 수 있다. 이는 관리자의 개입을 최소화하는 학습방법이면서 동시에 False Positive와 False Negative 의 오류를 매우 효율적으로 개선하는 방법으로 기대된다. 본 논문의 제안방법은 분석도구나 시스템에 의존하지 않기 때문에, 유사한 문제를 안고 있는 여러 분야의 네트웍 환경에 적용될 수 있다.더욱 높은성능을 가짐을 알 수 있다.의 각 노드의 전력이 위험할 때 에러 패킷을 발생하는 기법을 추가하였다. NS-2 시뮬레이터를 이용하여 실험을 한 결과, 제안한 기법이 AOMDV에 비해 경로 탐색 횟수가 최대 36.57% 까지 감소되었음을 알 수 있었다.의 작용보다 더 강력함을 시사하고 있다.TEX>로 최고값을 나타내었으며 그 후 감소하여 담금 10일에는 $1.61{\sim}2.34%$였다. 시험구간에는 KKR, SKR이 비교적 높은 값을 나타내었다. 무기질 함량은 발효기간이 경과할수록 증하였고 Ca는 $2.95{\sim}36.76$, Cu는 $0.01{\sim}0.14$, Fe는 $0.71{\sim}3.23$, K는 $110.89{\sim}517.33$, Mg는 $34.78{\sim}122.40$, Mn은 $0.56{\sim}5.98$, Na는 $0.19{\sim}14.36$, Zn은 $0.90{\sim}5.71ppm$을 나타내었으며, 시험구별로 보면 WNR, BNR구가 Na만 제외한 다른 무기성분 함량이 가장 높았다.O to reduce I/O cost by reusing data already present in the memory of other nodes. Finally, chunking and on-line compression mechanisms are included in both models. We demonstrate that we can obtain significantly high-performanc