• Korean Management Science Review
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• v.26 no.1
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• pp.171-182
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• 2009

We consider the inventory replenishment problem and the vehicle routing problem simultaneously in the vending machine operation. This problem is known as the inventory routing problem. We design a memory cell in the clonal selection algorithm. The memory cell store the best solution of previous solved problem and use an initial solution for next problem. In general, the other clonal selection algorithm used memory cell for reserving the best solution in current problem. Experiments are performed for testing efficiency of the memory cell in demand uncertainty. Experiment result shows that the solution quality of our algorithm is similar to general clonal selection algorithm and the calculations time is reduced by 20% when the demand uncertainty is less than 30%.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.2
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• pp.98-113
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• 2009

Conventional file systems for harddisk drive cannot be applied to NAND flash memory, because the physical characteristics of NAND flash memory differs from those of harddisk drive. To address this problem, various file systems with better reliability and efficiency have also been developed recently. However, those file systems have inherent overheads for updating the file's metadata pages, because those file systems save file's meta-data and data separately. Furthermore, those file systems have a critical reliability problem: file systems fail when either a page in meta-data of a file system or a file itself fails. In this paper, we propose a self-description page technique and In Memory Core File System technique to address these efficiency and reliability problems, and develop SDFS(Self-Description File System) newly. SDFS can be safely recovered, although some pages fail, and improves write and read performance by 36% and 15%, respectively, and reduces mounting time by 1/20 compared with YAFFS2.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.9 no.3
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• pp.747-756
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• 2019

Students studying interpretation perform additional study and training in addition to regular class. In simultaneous interpreting and consecutive interpreting, interpreter should memorize speaker's announcement because of different language structure. To improve short-term memory, students perform memory training that requires a pair of students. Therefore, they can not perform self-learning, and therefore, efficiency of studying decreases. To resolve this problem, computer based short-term memory training system has been proposed. Student can perform self-learning by changing words in text to special character in the training system. However, efficiency of studying decreases because computer has low portability. Since the number of words is larger than the number of words to be switched into special character, learning difficulty decreases. To resolve this problem, smart device based short-term memory training system has been proposed. Student can perform smart device based training system without space constraints. Since the proposed training system increases the number of words to be changed into special character, learning difficulty increases. We implemented and evaluated the functionalities of the proposed training system.

• Journal of the military operations research society of Korea
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• v.14 no.1
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• pp.1-17
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• 1988

This paper presents a hardware accelerator for the maze routing problem. This accelerator consists of three 3 stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency.

• Journal of the military operations research society of Korea
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• v.13 no.2
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• pp.1-17
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• 1987

This paper presents a hardware accelerator for the maze routing problem. This accelerator consists of three 3 stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.8
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• pp.927-936
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• 1988

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.89-94
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• 1989

In this paper, we propose a hybrid optical/digital version of the associative memory which improve hardware efficiency and increase convergence rates. Multifocus hololens are used as space-varient optical element for performing inner product and summation function. The real-time input and the stored states of memory matrix is formated using LCTV. One method of adaptively changing the weights of stored vectors during each iteration is implemented electronically. A design for a optical implementation scheme is discussed and the proposed architecture is demonstrated the ability of retrieving with computer simmulation.

• Transactions on Electrical and Electronic Materials
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• v.6 no.6
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• pp.276-279
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• 2005

Influences of sustain pulse-width on electrical characteristics and luminous efficiency are experimentally investigated for surface discharge of AC-PDP. A square pulse with variable duty ratio and fixed rising time of 300 ns has been used in the experiment. It is found that the memory coefficient is significantly increased at the critical pulse-width. And the wall charges and wall voltages as well as capacitances are experimentally measured by Q- V analysis method along with the voltage margin relation, in terms of the sustain pulse-width in the range of $1{\mu}s$ to $5{\mu}s$ under driving frequency of 10 kHz to 180 kHz. And the luminous efficiency is also experimentally investigated in above range of sustain pulse-width with driving frequency of 10 kHz to 180 kHz. It is noted that the luminous efficiency for 10 kHz and 180 kHz are 1.29 1m/W and 0.68 1m/W respectively, since the power consumption for 10 kHz is much less than that for 180 kHz. It has been concluded that the optimal sustain pulse-width is in the range of $2.5 {\~}4.5{\mu}s$ under driving frequency range of 10 kHz and 60 kHz, and in the range of $1.5 {\~} 2.5{\mu}s$ under driving frequency range of 120 kHz and 180 kHz based on observation of memory coefficient, and wall voltage as well as luminous efficiency.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.377-384
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• 2007

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper, We proposed a reallocation algorithm for faulty memory part to efficient reallocation with row and column redundant memory. Reallocation information obtained from faulty memory by only every test. Time overhead problem occurs geting reallocation information as every test. To its avoid, one test resulted from reallocation information can save to flash memory. In this paper, reallocation information increases efficiency using flash memory.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.281.2-281.2
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• 2016

Two-dimensional van der Waals (2D vdWs) materials have been extensively studied for future electronics and materials sciences due to their unique properties. Among them, black phosphorous (BP) has shown infinite potential for various device applications because of its high mobility and direct narrow band gap (~0.3 eV). In this work, we demonstrate a few-nm thick BP-based nonvolatile memory devices with an well-known poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] ferroelectric polymer gate insulator. Our BP ferroelectric memory devices show the highest linear mobility value of $1159cm^2/Vs$ with a $10^3$ on/off current ratio in our knowledge. Moreover, we successfully fabricate the ferroelectric complementary metal-oxide-semiconductor (CMOS) memory inverter circuits, combined with an n-type $MoS_2$ nanosheet transistor. Our memory CMOS inverter circuits show clear memory properties with a high output voltage memory efficiency of 95%. We thus conclude that the results of our ferroelectric memory devices exhibit promising perspectives for the future of 2D nanoelectronics and material science. More and advanced details will be discussed in the meeting.