• Journal of the Korean Institute of Intelligent Systems
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• v.20 no.6
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• pp.761-767
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• 2010

In the case of NAND flash memory, a whole block needs to be erased for update operations because update-in- place operations are not supported in NAND flash memory. Blocks of NAND flash memory have the limited erasure cycles, so frequently updated data (hot data) easily makes blocks worn out. As the result, the capacity of NAND flash memory will be reduced by hot data. In this paper, we propose a wear-leveling algorithm by discriminating hot and cold data based on the update patterns of data. When we applied this scheme to NAND flash memory, we confirmed that the erase counts of blocks became more uniform by mapping hot data to a block with a low erase count and cold data to block with a high erase count.

• Journal of Digital Contents Society
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• v.14 no.2
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• pp.247-254
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• 2013

Storage Class Memory(SCM), such as PRAM, FRAM and MRAM, are expected to be comparable to DRAM in terms of access speed and to Flash memory in terms of capacity in a near future. In this paper, assuming that not only the secondary storage (HDD or Flash memory) but also the primary memory (DRAM) will be replaced by SCM in the future computer systems, we propose an efficient file access framework for the SCM based computer systems. The proposed framework do not assign exclusive area in the SCM to the file system and uses various memory-related techniques, such as unified data access path, zero-copy data read using file mapping, copy-on-write, and multiple page pre-faulting for file management. Based on the preliminary experimental results, we could conclude that the proposed framework can be an efficient baseline for designing a new operating system for the SCM based computer systems.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.8
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• pp.1962-1969
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• 2009

During past 20 years we have witnessed brilliant advances in major components of computer system, including CPU, memory, network device and HDD. Among these components, in spite of its tremendous advance in capacity, the HDD is the most performance dragging device until now and there is little affirmative forecasting that this problem will be resolved in the near future. We present a new approach to solve this problem using the NAND Flash memory. Researches utilizing Flash memory as storage medium are abundant these days, but almost all of them are targeted to mobile or embedded devices. Our research aims to develop the NAND Flash memory based storage system enough even for enterprise level server systems. This paper present structural and operational mechanism to overcome the weaknesses of existing NAND Flash memory based storage system, and its evaluation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.1
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• pp.31-36
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• 2024

Recently, mobile apps that utilize AI technologies are increasing. In the personal mobile environment, performance degradation may occur during the training phase of large AI workload due to limitations in memory capacity. In this paper, we extract memory reference traces of AI workloads and analyze their characteristics. From this analysis, we observe that AI workloads can cause frequent storage access due to weak temporal locality and irregular popularity bias during memory write operations, which can degrade the performance of mobile devices. Based on this observation, we discuss ways to efficiently manage memory write operations of AI workloads using persistent memory-based swap devices. Through simulation experiments, we show that the system architecture proposed in this paper can improve the I/O time of mobile systems by more than 80%.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.91-95
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• 2017

Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.

• Journal of the Korea Society of Computer and Information
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• v.25 no.3
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• pp.51-55
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• 2020

In this paper, an improved FAM is proposed by adopting similarity learning in the existing FAM (Fuzzy Associative Memory) used in image restoration. Image restoration refers to the recovery of the latent clean image from its noise-corrupted version. In serious application like face recognition, this process should be noise-tolerant, robust, fast, and scalable. The existing FAM is a simple single layered neural network that can be applied to this domain with its robust fuzzy control but has low capacity problem in real world applications. That similarity measure is implied to the connection strength of the FAM structure to minimize the root mean square error between the recovered and the original image. The efficacy of the proposed algorithm is verified with significant low error magnitude from random noise in our experiment.

• Structural Engineering and Mechanics
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• v.64 no.1
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• pp.109-120
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• 2017

The behavior of moment resistant steel structures depends on both the beam-column connections and columns foundations connections. Obviously, if the connections can meet the adequate ductility and resistance against lateral loads, the seismic capacity of these structures will be linked practically to the performance of these connections. The shape memory alloys (SMAs) have been most recently used as a means of energy dissipation in buildings. The main approach adopted by researchers in the use of such alloys is firstly bracing, and secondly connecting the beams to columns. Additionally, the behavior of these alloys is modeled in software applications rarely involving equivalent torsional springs and column-foundation connections. This paper attempts to introduce the shape memory alloys and their applications in steel structural connections, proposing a new steel column-foundation connection, not merely a theoretical model but practically a realistic and applicable model in structures. Moreover, it entails the same functionality as macro modeling software based on real behavior, which can use different materials to establish a connection between the columns and foundations. In this paper, the suggested steel column-foundation connection was introduced. Moreover, exploring the seismic dynamic behavior under cyclic loading protocols and the famous earthquake records with different materials such as steel and interconnection equipment by superelastic shape memory alloys have been investigated. Then, the results were compared to demonstrate that such connections are ideal against the seismic behavior and energy dissipation.

• Smart Structures and Systems
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• v.15 no.6
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• pp.1521-1542
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• 2015

The use of shape memory alloys (SMAs) in dynamical systems has an increasing importance in engineering especially due to their capacity to provide vibration reductions. In this regard, experimental tests are essential in order to show all potentialities of this kind of systems. In this work, SMA springs are incorporated in a dynamical system that consists of a one degree of freedom oscillator connected to a linear spring and a mass, which is also connected to the SMA spring. Two types of springs are investigated defining two distinct systems: a pseudoelastic and a shape memory system. The characterisation of the springs is evaluated by considering differential calorimetry scanning tests and also force-displacement tests at different temperatures. Free and forced vibration experiments are made in order to investigate the dynamical behaviour of the systems. For both systems, it is observed the capability of changing the equilibrium position due to phase transformations leading to hysteretic behaviour, or due to temperature changes which also induce phase transformations and therefore, change in stiffness. Both situations are investigated by promoting temperature changes and also pre-tension of the springs. This article shows several experimental tests that allow one to obtain a general comprehension of the dynamical behaviour of SMA systems. Results show the general thermo-mechanical behaviour of SMA dynamical systems and the obtained conclusions can be applied in distinct situations as in rotor-bearing systems.

• PNF and Movement
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• v.14 no.1
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• pp.41-47
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• 2016

Purpose: In general, confabulation is defined as confusion of reality with past events without apparent prompting, in association with disruption of the capacity for retrieval and encoding of memory. We report on a patient who showed spontaneous confabulation associated with injury of the Papez circuit following middle cerebral artery (MCA) infarction. Methods: A 67-year-old female patient suffered cerebral infarct resulting from spontaneous MCA territory. After onset of the MCA infarct, she showed severe memory impairment and provoked confabulation. The Papez circuit was reconstructed for evaluation of part of it using diffusion tensor tractography (DTT). Fractional anisotropy (FA), mean diffusivity (MD), and tract volume were measured. Results: The right thalamocingulate tract showed a significant decrement of FA value and tract volume, and an increment of MD value by more than two standard deviations of that of normal control subjects. The tract volume in the left fornix and mammillothalamic tract decreased by more than two standard deviations of that of normal control subjects. Conclusion: Injuries of the Papez circuit were demonstrated in a patient who showed severe memory impairment and provoked confabulation following MCA infarct. We believe that analysis of the Papez circuit tract using DTT is useful in elucidating the cause of provoked confabulation in patients with MCA infarct.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.