• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.55-60
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• 2011

Most of neural network chips use an analog-type maximum selector circuit (MS). As the increase of integration level, the analog MS has difficulties in achieving sufficient resolution. Contrary, the digital-type MS is easy to get high resolution but slower than its analog counterparts. A new high-speed digital MS circuit called MSIT (Maximum Selector with Internal Trigger-signal) is presented in this paper. The MSIT has been designed to achieves both the high reliability by using trigger-signals and high speed by removing the unnecessary waiting times. The response time of MSIT is 3.4ns for 32 data with 10-bit resolution in the simulation with 1.2V, $0.13{\mu}m$-process model parameters, which is much faster than its analog counterparts. It shows that digital MS circuits like MSIT can achieve higher speed as well as higher resolution than analog MS circuits.

• Archives of Pharmacal Research
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• v.27 no.9
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• pp.973-977
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• 2004

Carvedilol is administered as a racemic mixture of the R(＋)- and S(-)-enantiomers, although they exhibit different pharmacological effects. To investigate the stereoselective pharmacoki-netics, the enantiomeric separation of carvedilol in human plasma was undertaken using capil-lary electrophoresis (CE). Resolution of the enantiomers was achieved using 2-hydoxypropyl-$\beta$-cyclodextrin as the chiral selector. Phosphate buffer (50 mM, pH 4.0) containing 10 mM of 2-hydoxypropropyl-$\beta$-cyclodextrin was used as electrolytic buffer. Achiral separation was carried out with the same electrolytic buffer without chiral selector. Following a single oral administra-tion of 25-mg carvedilol to 11 healthy, male volunteers, stereoselective pharmacokinetic analy-sis was undertaken. The maximum plasma concentrations ( $C_{max}$) were 48.9 and 21.6 ng/mL for (R)-carvedilol and (S)-carvedilol, respectively, determined by the chiral method. The profiles of the plasma concentration of (RS)-carvedilol showed $C_{max}$ of 71.5, 72.2, and 73.5 ng/mL, as determined by the CE, HPLC/FD methods and calculations from the data of the chiral method, respectively.y.y.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1684-1692
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• 2016

In order to adapt the fast dynamic performances of Buck DC/DC converter, and reduce the influence on converter performance owing to uncertain factors such as the disturbances of parameters and load, a control strategy based on two-dimensional hybrid cloud model is proposed. Firstly, two cloud models corresponding to the specific control inputs are determined by maximum determination approach, respectively, and then a control rule decided by the two cloud models is selected by a rule selector, finally, according to the reasoning structure of the rule, the control increment is calculated out by a two-dimensional hybrid cloud decision module. Both the simulation and experiment results show that the strategy can dramatically improve the dynamic performances of the converter, and enhance the adaptive ability to resist the random disturbances, and its control effect is superior to that of the current-mode control.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.10
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• pp.1109-1116
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• 1992

Mathematical morphology, theoretical foundation for morphological filter, is very efficient for the analysis of the geometrical characteristics of signals and systems and is used as a predominant tool for smoothing the data with noise. In this study, H/W design of morphological filter is implemented to process the gray scale dilation and the erosion in the same circuit and to choose the maximum and minimum value by a selector, resulting in their education of the complexity of the circuit and an architecture for parallel processing. The structure of morphological filter consists of the structuring-element block, the image data block, the control block, the ADD block, the MIN/MAX block, etc, and is designed on an one-chip for real time operation.

• Bulletin of the Korean Chemical Society
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• v.25 no.3
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• pp.377-381
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• 2004

Chiral separation of aryalcohols such as 1-phenyl-propanol, 1-phenyl-2-proanol, and 2-phenyl-1-propanol by capillary electrophoresis has been optimized using the overlapping resolution mapping (ORM) scheme. Three critical parameters of the electrophoretic media, i.e. phosphate concentration, sulfated ${\beta}$-cyclodextrin (CD) concentration and pH, were chosen for optimization. The working ranges were initially presumed by 7 preexperiments. Further optimization was carried out by another seven experiments within the narrow working ranges. From the final overlapping resolution mapping all peak pairs, the area of maximum separations were located. Using the conditions of a point in this area, we found that the target compounds were a baseline separated within 30 min. The maximum separation conditions of arylalcohols were a chiral selector concentration of 5.4%, a phosphate concentration of 28 mM, and a pH of 5.0.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.141-146
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• 2016

This paper presents a method to improve time interval error for asynchronous communication systems. The proposed method is designed and simulated with multi-phase VCO, interpolator, phase selector, up-down counter, comparator and adder. The simulation results for CAN communication system show that the maximum time interval error can be tightly managed for satisfying the required specification. The proposed frequency modulation method can be properly used for asynchronous communication systems requiring high reliability.

• Journal of KIISE:Software and Applications
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• v.35 no.2
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• pp.91-104
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• 2008

Service-Oriented Computing (SOC) is the development method that published services are selected and composed at runtime to deliver the expected functionality to service clients. SOC should get maximum benefits not only supporting business agility but also reducing the development time. Services are selected and composed at runtime to improve the benefits. However, current programming language, SOC platforms, business process modeling language, and tools support either manual selection or static binding of published services. There is a limitation on reconfiguring and redeploying the business process to deliver the expected services to each client. Therefore, dynamic selection is needed for composing appropriate services to service clients in a quick and flexible manner. In this paper, we propose Dynamic Selection Handler (DSH) on ESB. we present a design method of Dynamic Selection Handler which consists of four components; Invocation Listener, Service Selector, Service Binder and Interface Transformer. We apply appropriate design patterns for each component to maximize reusability of components. Finally, we describe a case study that shows the feasibility of DSH on ESB.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.6
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• pp.29-36
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• 2015

This paper presents an LED backlight driver IC consisting of three linear current regulators and an output-voltage regulation loop with a self-adjustable reference voltage. In the proposed LED driver, the output voltage is controlled by dual feedback loops. The first loop senses and controls the output voltage, and the second loop senses the voltage drop of the linear current regulator and adjusts the reference voltage. With these feedback loops, the voltage drop of the linear current regulator is maintained at a minimum value, at which the driver efficiency is maximized. The output of the driver is a three-channel LED setup with four LEDs in each channel. The luminance is adjusted by the PWM dimming signal. The proposed driver is designed by a $0.35-{\mu}m$ 60-V high-voltage process, resulting in an experimental maximum efficiency of approximately 85%.