• Title/Summary/Keyword: Max throughput

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Proteomic Characterization of the 'Agakong', a Small-seeded Recombinant Inbred Line Derived from 'Eunhakong' (Glycine max) $\times$ 'KLG10084' (Glycine soja)

  • Choi, Ung-Kyu;Ryu, Hyun-Su;Kim, Hyun-Tae;Yun, Sun-Mi;Lee, Su-Jin;Choi, Jae-Dek;Hwang, Young-Hyun;Choi, Soo-Young;Kwon, Oh-Shin
    • Food Science and Biotechnology
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    • v.17 no.5
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    • pp.912-918
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    • 2008
  • This study was conducted to identify the differences in proteomic characteristics of 'Agakong', recombinant inbred line, and its parental genotypes 'Eunhakong' (Glycine max) and 'KLG10084' (G. soja). The isoflavone content of 'Agakong' was 3 times higher than that of its parental lines. A combined high-throughput proteomic approach was employed to determine the expression profile and identity of proteins using 2-dimensional gel electrophoresis and matrix-assisted laser desorption ionization time-of-flight (MALDI-TOF) mass spectrometry. The overall distribution patterns of proteins are quite similar, but lots of protein spot intensities varied among the genotypes. A total of 41 proteins, representing significant difference in the quantities of protein among the lines, were successfully identified. Among them, more than 50% of the proteins identified were subunits of glycinin and $\beta$-conglycinin, 2 major storage proteins. This study showed that the proteomic analysis could help to define specific changes in protein level and composition, which can occur in the generation of new soybean varieties.

A Study on the Design of Switch for High Speed Internet Communication Network (고속 인터넷 통신망을 위한 스위치 설계에 관한 연구)

  • 조삼호
    • Journal of Internet Computing and Services
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    • v.3 no.3
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    • pp.87-93
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    • 2002
  • A complex network and a parallel computer are made up of interconnected switching units. The role of a switching unit is to set up a connection between an input port and an output port, according to the routing information. We proposed our switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. We have analysed the maximum throughput of the revised switch. Our analyses have shown that under the uniform random traffic load, the FIFO discipline is limited to 70%, The switching system consists of an input control unit, a switch unit and an output control unit. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt the new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased by about 11% when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL using Max+plusII. We also designed our test environment including micro computers, the base station, and the proposed architecture. We proposed a new architecture of the Banyan switch for BISDN networks and parallel computers.

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Mobility-Aware Interference Avoidance Scheme for Vehicular WLANs

  • Park, Lai-Hyuk;Na, Woong-Soo;Lee, Gun-Woo;Lee, Chang-Ha;Park, Chang-Yun;Cho, Yong-Soo;Cho, Sung-Rae
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.5 no.12
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    • pp.2272-2293
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    • 2011
  • Communication technology of future networks is predicted to provide a large variety of services including WiFi service in vehicular network. In this paper, we assume that vehicles are embedded with WiMAX antenna and in-vehicle terminals receive WiMAX traffic through WiFi interface. This assumption will impose severe performance degradation due to interference among mobile BSSs when WiFi access points (APs) are densely located. Existing interference avoidance techniques cannot properly resolve the above problems and do not cope with dynamically moving vehicular scenario since they focus only on the fixed network topology. In this paper, we propose a mobility-aware interference avoidance scheme for WiFi services. The proposed scheme computes the interference duration by exploiting mobility vector and location information of neighboring APs. If the interference duration is not negligible, our scheme searches for another channel in order to avoid interference. However, if the interference duration is negligible, our scheme continues to use the channel to reduce switching overhead. To measure the effectiveness of the proposed scheme against other existing techniques, we evaluated performance by using OPNET simulator. Through the simulation, we obtained about 60% reduction in the maximum interference frequency and about 67% improvement in throughput. Furthermore, our scheme provides fair channel usage.

Implementation of a FLEX Protocol Signal Processor for High Speed Paging System (고속 페이징 시스템을 위한 FLEX 프로토콜 신호처리기의 구현)

  • Gang, Min-Seop;Lee, Tae-Eung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.69-78
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    • 2001
  • This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

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Performance Analysis of Flow Control Method Using Virtual Switchs on ATM (ATM에서 가상 스위치를 이용한 흐름 제어 방식의 성능 분석)

  • 조미령;양성현;이상훈
    • Journal of the Korea Computer Industry Society
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    • v.3 no.1
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    • pp.85-94
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    • 2002
  • EMRCA(Explicit Max_min Rate Control Algorithm) switch, which has been proposed in the ATM(Asychronous Transfer Mode) standard, controls the ABR(Available Bit Rate) service traffic in the ATM networks. The ABR service class of ATM networks uses a feedback control mechanism to adapt to varying link capacities. The VS/VD(Virtual Source/Virtual Destination) technique offers the possibility to segment the otherwise end-to-end ABR control loop into separate loops. The improved feedback delay and the control of ABR traffic inside closed segments provide a better performance and QoS(Quality of Service) for ABR connections with respect to throughput, delay, and jitter. This paper is study of an ABR VS/VD flow control method. Linear control theory offers the means to derive correct choices of parameters and to assess performance issues, like stability of the system, during the design phase. The performance goals are a high link utilization, fair bandwidth distribution and robust operation in various environments, which are verified by discrete event simulations. The major contribution of this work is the use of linear control theory to model and design an ABR flow control method tailored for the special layout of a VS/VD switch, the simulation shows that this techniques better than conventional method.

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On a High-Speed Implementation of LILI-128 Stream Cipher Using FPGA/VHDL (FPGA/VHDL을 이용한 LILI-128 암호의 고속화 구현에 관한 연구)

  • 이훈재;문상재
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.3
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    • pp.23-32
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    • 2001
  • Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

A Joint Resource Allocation Scheme for Relay Enhanced Multi-cell Orthogonal Frequency Division Multiple Networks

  • Fu, Yaru;Zhu, Qi
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.7 no.2
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    • pp.288-307
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    • 2013
  • This paper formulates resource allocation for decode-and-forward (DF) relay assisted multi-cell orthogonal frequency division multiple (OFDM) networks as an optimization problem taking into account of inter-cell interference and users fairness. To maximize the transmit rate of system we propose a joint interference coordination, subcarrier and power allocation algorithm. To reduce the complexity, this semi-distributed algorithm divides the primal optimization into three sub-optimization problems, which transforms the mixed binary nonlinear programming problem (BNLP) into standard convex optimization problems. The first layer optimization problem is used to get the optimal subcarrier distribution index. The second is to solve the problem that how to allocate power optimally in a certain subcarrier distribution order. Based on the concept of equivalent channel gain (ECG) we transform the max-min function into standard closed expression. Subsequently, with the aid of dual decomposition, water-filling theorem and iterative power allocation algorithm the optimal solution of the original problem can be got with acceptable complexity. The third sub-problem considers dynamic co-channel interference caused by adjacent cells and redistributes resources to achieve the goal of maximizing system throughput. Finally, simulation results are provided to corroborate the proposed algorithm.

Development and Application of High-density SNP Arrays in Genomic Studies of Domestic Animals

  • Fan, Bin;Du, Zhi-Qiang;Gorbach, Danielle M.;Rothschild, Max F.
    • Asian-Australasian Journal of Animal Sciences
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    • v.23 no.7
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    • pp.833-847
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    • 2010
  • In the past decade, there have been many advances in whole-genome sequencing in domestic animals, as well as the development of "next-generation" sequencing technologies and high-throughput genotyping platforms. Consequently, these advances have led to the creation of the high-density SNP array as a state-of-the-art tool for genetics and genomics analyses of domestic animals. The emergence and utilization of SNP arrays will have significant impacts not only on the scale, speed, and expense of SNP genotyping, but also on theoretical and applied studies of quantitative genetics, population genetics and molecular evolution. The most promising applications in agriculture could be genome-wide association studies (GWAS) and genomic selection for the improvement of economically important traits. However, some challenges still face these applications, such as incorporating linkage disequilibrium (LD) information from HapMap projects, data storage, and especially appropriate statistical analyses on the high-dimensional, structured genomics data. More efforts are still needed to make better use of the high-density SNP arrays in both academic studies and industrial applications.

기체부하에 대한 크라이오 펌프의 성능 평가 방안

  • In, Sang-Ryeol;Jeong, Seung-Ho
    • Proceedings of the Korean Vacuum Society Conference
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    • 2010.02a
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    • pp.333-333
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    • 2010
  • 크라이오 펌프는 크기에 비해 상대적으로 큰 배기속도를 가지고 있고 자체 기체 방출이 적어 비교적 쉽고 빠르게 도달압력을 낮출 수 있다. 또 초고진공 펌프로서 경쟁 상대인 터보분자 펌프보다 기체 돌입에 대한 기계적 사고 가능성이 낮다. 그러나 흡착 패널의 온도에 민감하게 반응하는 배기 성능 측면에서 볼 때 크라이오 펌프의 대유량 및 펄스 기체 부하에 대한 성능 유지 및 회복능력은 의문의 여지가 있다. 크라이오 펌프의 기체부하에 대한 공식적인 성능지표로는 최대배기량(max. throughput)과 교차(crossover)값이 있다. 전자는 연속적인 유량[$Pa{\cdot}m^3/s$]에 대해, 또 후자는 일정 기체량[$Pa{\cdot}m^3$]에 대해 흡착 패널이 20 K를 넘지 않는 가동범위를 구하는 것이다. 교차값은 넓은 의미에서 펄스 기체부하에 대한 성능으로 볼 수도 있지만 원래 목적은 진공용기를 저진공 상태에서 고진공 상태로 전환하는 시점을 정하려는 데 있다. 펌프회사에서 제공하는 사양에는 대부분 아르곤 회복시간(Ar recovery time)이라는 지표가 있는데 이는 아르곤을 상당한 유량으로 흘리다 멈췄을 때 얼마나 빨리 기저 상태로 회복되는가를 나타낸다. 보통 사양서에 제시하지는 않지만 주로 크라이오 펌프의 재생상태를 알아보기 위해 사용하는 걸프(gulp) 시험이 있는데 일정량의 기체를 펄스로 도입한 후 압력변화를 기록하여 재생후 배기성능 회복 능력을 보는 것이다. 이들은 겉보기에 서로 다르지만 한편으로는 서로 중복되거나 연관성을 가지고 있어서 실용적인 면에서 절차들을 비교, 검토 및 개선하고 때에 따라서는 적절히 결합할 수 있는 방안을 모색할 필요성이 있다.

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A study of Vertical Handover between LTE and Wireless LAN Systems using Adaptive Fuzzy Logic Control and Policy based Multiple Criteria Decision Making Method (LTE/WLAN 이종망 환경에서 퍼지제어와 정책적 다기준 의사결정법을 이용한 적응적 VHO 방안 연구)

  • Lee, In-Hwan;Kim, Tae-Sub;Cho, Sung-Ho
    • The KIPS Transactions:PartC
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    • v.17C no.3
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    • pp.271-280
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    • 2010
  • For the next generation mobile communication system, diverse wireless network techniques such as beyond 3G LTE, WiMAX/WiBro, and next generation WLAN etc. are proceeding to the form integrated into the All-IP core network. According to this development, Beyond 3G integrated into heterogeneous wireless access technologies must support the vertical handover and network to be used of several radio networks. However, unified management of each network is demanded since it is individually serviced. Therefore, in order to solve this problem this study is introducing the theory of Common Radio Resource Management (CRRM) based on Generic Link Layer (GLL). This study designs the structure and functions to support the vertical handover and propose the vertical handover algorithm of which policy-based and MCDM are composed between LTE and WLAN systems using GLL. Finally, simulation results are presented to show the improved performance over the data throughput, handover success rate, the system service cost and handover attempt number.