• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(5)
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• pp.181-184
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• 2001

This paper has been studied driving circuits in electrical valves. Also in this paper, opto-couplers of driving circuit are replaced with digital one chip of Altera company. Designs in order to realization of one chip are carried out with Altera Max Plus II. For compact size and light weight, the realization with one chip is necessary in the electrical valves. This paper has designed and presented the digital schemetic circuits, finally the driving circuits are sucessfully operated with the designed chip and showed the saving of area in the driving circuits of electric valves.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1032-1034
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• 2001

As well known, a solar cell has an optimal operating point to be able to get the maximum power $P_{max}$. So, many $P_{max}$ tracking controllers using the line voltage of a solar cell have been popularly used. But it may vary depending on the miss match between the solar cell output and the load. In this paper, we investigate the possibilities of $P_{max}$ control using the current tracking controller and the output voltage and the output current instead of the solar cell output power. And we also examine about the optimal power converter using ZVCS step up and down chopper circuit to operate the solar cell at an optimal voltage using these variables. And then, we show some experimental results to confirm the successful operation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 B
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• pp.976-978
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• 1999

Recently PWM invertor is broadly used for control of induction motor. The invertor is able to generate sin wave current from high speed switching power device such as IGBT. However the invertor is disturbed by dead time inevitably needed to prevent a short of the DC link voltage, and the dead time mainly causes distortions of the output current. In this Paper the dead time compensation method which corrects the voltage error from dead time, and Min Max algorithm enlarging the operating voltage of PWM were Proposed. This method can be implemented by software programming without any additional hardware circuit. The proposed algorithms were implemented by DSP(TMS320C31, 40MHz) and FPGA(QL2007, Quick Logic) described in VHDL. and applied to 3 phase induction motor(2.2 KW) to show the superior performance

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.105.3-105
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• 2001

In this paper, a current mode two-input maximum (Max) and minimum (Min) operations scheme, which is a useful building block for analog fuzzy inference systems, is presented. The Max and Min operations are incorporated in the same scheme with parallel processing. The proposed scheme comprises a MOS class AB/B configuration and current mirrors. Its simple structure can provide a high efficiency. The performance of the scheme exhibits a very sharp transfer characteristic and high accuracy. The proposed scheme achieves a high-speed operation and is suitable for real-time systems. The simulation results verifying the performances of the scheme are agreed with the expected values.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.377-387
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• 2012

An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.968-971
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• 1993

Fuzzy inference system which inferences and processes the Fuzzy information is designed using digital voltage mode neural circuits. The digital fuzzification circuit is designed to MIN,MAX circuit using CMOS neural comparator. A new defuzzification method which uses the center of area of the resultant fuzzy set as a defuzzified output is suggested. The method of the center of area(C. O. A) search for a crisp value which is correspond to a half of the area enclosed with inferenced membership function. The center of area defuzzification circuit is proposed. It is a simple circuit without divider and multiflier. The proposed circuits are verified by implementing with conventional digital chips.

• 한국정보통신학회논문지
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• 제20권1호
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• pp.117-122
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• 2016

본 논문에서는 차량 추돌 방지 단거리 레이더용 24-GHz CMOS 고주파 전력 증폭기 (RF power amplifier)를 제안한다. 이러한 회로는 클래스-A 모드 증폭기로서 단간 (inter-stages) 공액 정합 (conjugate matching) 회로를 가진 공통-소스 단으로 구성되어 있다. 제안한 회로는 TSMC $0.13-{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 설계하였다. 2볼트 전원전압에서 동작하며, 저전압 전원에서도 높은 전력 이득, 낮은 삽입 손실 및 낮은 음지수를 가지도록 설계되어 있다. 전체 칩 면적을 줄이기 위해 넓은 면적을 차지하는 실제 인덕터 대신 전송선(transmission line)을 이용하였다. 설계한 CMOS 고주파 전력 증폭기는 최근 발표된 연구결과에 비해 $0.1mm^2$의 가장 작은 칩 크기, 40mW의 가장 적은 소비전력, 26.5dB의 가장 높은 전력이득, 19.2dBm의 가장 높은 포화 출력 전력 및 17.2%의 가장 높은 최대 전력부가 효율 특성을 보였다.

• 한국전자파학회논문지
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• 제19권1호
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• pp.33-39
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• 2008

본 논문에서는 WiBro/WiMAX 대역(2.3${\sim}$3.5 GHz)에서 동작하는 광대역 $16(4{\times}4)$ 소자 배열 구형 반사판 안테나를 설계하고, 복사 특성을 고찰하였다. 설계된 안테나는 IBBD(Integrated Balun Bow-tie Dipole) 소자로 구성 되며, 급전 회로에서 발생하는 불요 전자파를 줄이기 위하여 반사판 뒷면에 급전 회로를 두었다. 설계된 안테나의 광대역 특성을 확인하기 위하여 실제 안테나를 제작하고 복사 특성을 측정하여 계산된 결과와 비교하였다. 측정결과는 계산 결과와 비슷하게 나타났으며, $2.06{\sim}3.89GHz$ 대역에서 VSWR 1.6 이하를 만족하였고, 안테나 이득은 사용 주파수 대역에서 10.3dBi 이상으로 나타났다. 따라서 본 논문에서 설계된 안테나는 WiBro/WiMAX 공용 배열 안테나로 사용할 수 있을 것으로 생각된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.262-264
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• 1996

This paper presents a new dual loop control using novel vector phase locked loop(VP-PLL) for a high power static var compensator(SVC) with three-level GTO voltage source inverter(VSI). Through circuit DQ-transformation, a simple dq-axis equivalent circuit is obtained. From this, DC analysis is carried out to obtain maximum controllable phase angle ${\alpha}_{max}$ per unit current between the three phase source and the switching function of inverter, and AC open-loop transfer function is given. Because ${\alpha}_{max}$ becomes small in high power SVC, this paper proposes VP-PLL for more accurate $\alpha$-control. As a result, the overall control loop has dual loop structure, which consists of inner VP-PLL for synchronizing the phase angle with source and outer Q-loop for compensating reactive power of load. Finally, the validity of the proposed control method is verified through the experimental results.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 추계학술대회
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• pp.415-418
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• 2011

WiMAX, WLAN 등의 무선통신 시스템에 사용되는 LDPC(low-density parity check) 복호기의 핵심 기능블록인 DFU(decoding function unit)의 회로 최적화를 제안한다. 최소합(min-sum) 복호 알고리듬 기반의 DFU는 2의 보수 값과 sign-magnitude 값 사이의 변환이 필요하여 회로가 복잡해진다. 본 논문에서는 sign-magnitude 연산 기반의 DFU를 설계하여 수체계 변환과정을 제거함으로써 회로를 간소화시키고 동작속도를 향상시켰다.