• Journal of Information Display
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• v.10 no.3
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• pp.111-116
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• 2009

In this paper, a plasma-assisted patterning method for the organic layers of organic light-emitting diodes (OLEDs) and its effect on the OLED performances are reported. Oxygen plasma was used to etch the organic layers, using the top electrode consisting of lithium fluoride and aluminum as an etching mask. Although the current flow at low voltages increased for the etched OLEDs, there was no significant degradation of the OLED efficiency and lifetime in comparison with the conventional OLEDs. Therefore, this method can be used to reduce the ohmic voltage drop along the common top electrodes by connecting the top electrode with highly conductive bus lines after the common organic layers on the bus lines are etched by plasma. To further analyze the current increase at low voltages, the plasma patterning effect on the OLED performance was investigated by changing the device sizes, especially in one direction, and by changing the etching depth in the vertical direction of the device. It was found that the current flow increase at low voltages was not proportional to the device sizes, indicating that the current flow increase does not come from the leakage current along the etched sides. In the etching depth experiment, the current flow at low voltages did not increase when the etching process was stopped in the middle of the hole transport layer. This means that the current flow increase at low voltages is closely related to the modification of the hole injection layer, and thus, to the modification of the interface between the hole injection layer and the bottom electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05a
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• pp.86-89
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• 2004

Organic thin film transistors (OTFTs) are fabricated on the plastic substrate through 4-level mask process without photolithographic patterning to yield the simple fabrication process. And we herewith report for the effect of dielectric surface modification on the electrical characteristics of OTFTs. The KIST-JM-1 as an organic molecule for the surface modification is deposited onto the surface of zirconium oxide $(ZrO_2)$ gate dielectric layer. In this work, we have examined the dependence of electrical performance on the interface surface state of gate dielectric/pentacene, which may be modified by chemical properties in the gate dielectric surface.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.31-40
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• 2005

The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of mobile computing applications. In this paper, we (i) motivate the post-mask-tooling performance enhancement technique combined with the MTCMOS leakage current suppression technology, and (ii) develop a practical MTCMOS ASIC design methodology which fine-tunes and integrates best-in-class techniques and commercially available tools to fix the new design issues related to the MTCMOS technology. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um Process. The fabricated PDA processor operates at 333MHz which has been improved about $23\%$ at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.1-5
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• 2000

Inductively coupled plasma (ICP) excited by a spiral planar antenna is used to etch elctrodes for PZT capacitors. Pt/RuO$_{2}$ bilayers are tested as bottom electrodes for PZT capacitors in order to utilize better leakage characteristics of Pt and easy etch characteristics of RuO$_{2}$ at the same time. The etch rates and selectivities to SiO$_{2}$ hard mask have been measured for each of Pt and RuO$_{2}$ in terms of various plasma conditions. As Cl$_{2}$ ratio increases in $O_{2}$/Cl$_{2}$ mixture, the etch rate of Pt increases while that of RuO$_{2}$ reaches the highest near 10 ％ of Cl$_{2}$. Optimum gas mixture ratio has been determined for etching Pt and RuO$_{2}$ bilayers sequentially, and sub-half micron patterning is demonstrated.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.39-44
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• 2005

The OFDM modulation and transmission block have been modeled in order to analyse the relationship between the 2.4GHz power amplifier distortion and output ACPR for the IEEE 802.11g wireless LAN. The nonlinear characteristic of the power amplifier has been modeled as AM-to-AM and AM-to-PM using the behavioral model, and the output spectrum is analysed with the phase distortion variation. Also, amplifier back-off value from P1dB to satisfy the required IEEE 802.11g standard spectrum mask s been simulated with modeled phase distortion, and the simulation data have been compared to the measured result by using the pre-distortion technique.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.107-115
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• 1998

A multiplier bit-pair recoding technique derived from Booth algorithm is used as an effective method that can carry out a fast binary multiplication regardless of a sign of both multiplicand and multiplier. In this paper, we propose an implementation of an optical high-speed multiplier which consists of a symbolic substitution adder and an optical multiplication algorithm, which transforms and enhances the multiplier bit-pair recoding algorithm to be fit for optical characteristics. Specially, a symbolic substitution addition rules are coded with a dual-rail logic, and so the complement of the logic of the symbolic substitution adder is easily obtained with a shift operation because it is always present. We also construct the symbolic substitution system which makes superposition image by superimposing two shifted images in a serial connection and recognizes a reference image by feeding this superimposed image to a mask. Thus, the optical multiplier, which is compared with a typical system, is implemented to the smaller system by reducing the number of optical passive elements and the size of this system.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.114-119
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• 1996

The use of holographic interference lithography and removal techniques to corrugate GaAs substrate have been studied. The periodic photoresist structure, which serves as a protective mask during etching, is holographically prepared. Subsequently periodic V-grooved pattern is formed on the GaAs substrate by conventional a H$_{2}$SO$_{4}$-H$_{2}$O$_{2}$-H$_{2}$O wet etching. The linewidth of a GaAs pattern is about 0.4$\mu$m and the depth is 0.5$\mu$m A quantum wires(QWRs) array is well formed on the V-grooved substrate by MOCVD (metalorganic chemical vapor deposition) growth of GaAs/Al$_{0.5}$Ga$_{0.5}$As (50$\AA$/300$\AA$) quantum wells. The formation of QWR array is confirmed by the temperature dependent photoluminescence (PL) measurement. The intensive PL peak with a FWHM of 6meV at 21K shows the high quality of the QWR array.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.21-28
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• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.3
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• pp.1-6
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• 2008

A dual band I/Q modulator which converts baseband input signals to 2.4GHz or 5GHz RF output has been proposed. The dual band I/Q modulator for 2.4GHz and 5GHz wireless LAN applications consists of $90^{\circ}$ phase shifter and wideband mixer. The I/Q modulator showed 15dB conversion loss at 2.4GHz and 16dB conversion loss at 5GHz. The sideband suppression is about 15dBc at 2.4GHz and 16dBc at 5GHz. Measured data shows 8.5% EVM at 2.4GHz, and 10% EVM at 5GHz for QPSK with symbol rate of 11Mbps. A carrier rejection is about 40dBc at 2.4GHz/5GHz band, and the I/Q modulator satisfied the output wireless LAN spectrum mask with baseband input signal.