• Journal of KIISE
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• v.43 no.5
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• pp.524-530
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• 2016

The desire to access data faster and the growth of next-generation memories such as non-volatile memories, contribute to the development of research on memory file systems. It is recommended that memory mapped file I/O, which has less overhead than read-write I/O, is utilized in a high-performance memory file system. Memory mapped file I/O, however, brings a page table overhead, which becomes one of the big overheads that needs to be resolved in the entire file I/O performance. We find that same overheads occur unnecessarily, because a page table of a file is removed whenever a file is opened after being closed. To remove the duplicated overhead, we propose the mapping cache, a technique that does not delete a page table of a file but saves the page table to be reused when the mapping of the file is released. We demonstrate that mapping cache improves the performance of traditional file I/O by 2.8x and web server performance by 12%.

• Journal of the Korea Society of Computer and Information
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• v.22 no.7
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• pp.1-7
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• 2017

As the capacity of NAND flash module increases, the amount of RAM increases for caching and maintaining the FTL mapping information. In order to reduce the amount of mapping information managed in the RAM, a demand-based address mapping method stores the entire mapping information in the flash and some valid mapping information in the form of cache in the RAM so that the RAM can be used efficiently. However, when cache miss occurs, it is necessary to read the mapping information recorded in the flash, so overhead occurs to translate the address. If the RAM space is not enough, the cache hit ratio decreases, resulting in greater overhead. In this paper, we propose a method using two tables called TPMT(Translation Page Mapping Table) and SMT(Segmented Translation Page Mapping Table) to utilize both temporal locality and spatial locality more efficiently. A performance evaluation shows that this method can improve the cache hit ratio by up to 30% and reduces the extra translation operations by up to 72%, compared to the TPM scheme.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.10
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• pp.3135-3141
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• 1996

In order to develop an efficient algorithm for S-to-M mapping in CMCA, characteristics of CMCA mappings is studied and conceptual mapping procedure is physically described. Then, careful observations on the mapping procedure and experience reveal a simple algorithm of the S-to-M mapping. The algorithm is described and compared with other procedures for S-to-M mapping. It is found very efficient in terms of computational operations and processing time.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.371-375
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• 2010

SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.7 no.8
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• pp.2027-2041
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• 2013

In this paper, we propose a novel reversible data hiding scheme in the index tables of the vector quantization (VQ) compressed images based on index set construction strategy. On the sender side, three index sets are constructed, in which the first set and the second set include the indices with greater and less occurrence numbers in the given VQ index table, respectively. The index values in the index table belonging to the second set are added with prefixes from the third set to eliminate the collision with the two derived mapping sets of the first set, and this operation of adding prefixes has data hiding capability additionally. The main data embedding procedure can be achieved easily by mapping the index values in the first set to the corresponding values in the two derived mapping sets. The same three index sets reconstructed on the receiver side ensure the correctness of secret data extraction and the lossless recovery of index table. Experimental results demonstrate the effectiveness of the proposed scheme.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1759-1762
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• 2003

This paper proposes the method that design CLUT(color look-up table) simultaneously processing gamut mapping and color space conversion using only LUT without complex computation. After we construct LUT composed of scanner gamut and printer gamut, we extend L$\^$*/a$\^$*/b$\^$*/ points based on input L$\^$*/a$\^$*/b$\^$*/ to include input scanner L$\^$*/a$\^$*/b$\^$*/ Input RGB image of scanner is converted into CIEL$\^$*/a$\^$*/b$\^$*/ using regression (unction. CIELAB values of scanner are convened into CMY values including gamut mapping processing without additional gamut mapping using the proposed CLUT. In the experiments, the proposed method resulted in the similar color difference, but reduced the complexity computation compared with processing gamut mapping and color space conversion respectively

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1113-1119
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• 2002

In this paper, it was presented that broadly delivered scanner devices can also used in finger print recognition process and then modified existing steps of fingerprint image Processing. First, using the adaptive binary method, that effect was certified already, increased the effect of the results. And then, applying table mapping methods that looks for elements from look-up table, decreased the processing time, too. Finally, it was presented that ridge-direction characteristics extracted from these processes can used effectively In the area of fingerprint recognition system.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.125-134
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• 1994

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.386-390
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• 2002

In this paper, it was presented that broadly delivered scanner devices can also used in finger print recognition process and then modified existing steps of fingerprint image processing. First, using the adaptive binary method, that effect was certified already, increased the effect of the results. And then, applying table mapping methods that looks for elements from look-up table, decreased the processing time, too. Finally, it was presented that ridge-direction characteristics extracted from these processes can used effectively in the area of fingerprint recognition system.

• Journal of Korea Multimedia Society
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• v.6 no.1
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• pp.15-27
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• 2003

Recently, the volume of data is increasing rapidly in server for multimedia service, according to development of multimedia application environment. In recent research for storage technology the technology like of the SAN(Storage Area Network) advantages in scalibility of storage devices, and can read data from multiple disk arrays through RAID 0, 5. The RAID 0 and 5 translate to logical address to physical address using equation, but in case of adding disks at the system with equation -based mapping, the problem that we must rearrange the whole data in the previous disks happens. We use the mapping table to solve this problem in recent, but we can not load the whole mapping table in main memory because it occupies too large space. Therefore the extra I/Os are demanded to evaluate real physical address of data, so total performance of the system is degraded. In this paper, we propose the mapping method that supports the scalibility in RAID 0 or 5 system. The proposing method applies small metadata, so- called SZIT and simple equation, so it is possible that we make translate logical address to physical address rapidly and it is scalable in disk extending simultaneously Our suggesting method, if we add disks to the striping system for expanding of storage capacity, has an advantage of never stop service. So, SZlT-based mapping method can do online-disk-expanding in real-time service.