• Title/Summary/Keyword: Mapping Algorithm

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New Image Mapping Algorithm for 3D Integral Imaging Display System used in Virtual Reality

  • Suk, Myung-Hoon;Min, Sung-Wook
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07a
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    • pp.41-45
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    • 2005
  • A new algorithm of the image mapping which is a technique of the elemental image generation is proposed. The proposed method is based on the characteristics of the lens array such as the number, the size and the focal length of the elemental lens. The 3D image generated by 3D graphic API such as OpenGL can be directly adopted without the complex adaptation. Since the image mapping using the proposed method can enhance the speed of the elemental image generation, the computer- generated integral imaging system can be applied to virtual reality system.

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AN ITERATIVE ALGORITHM FOR ASYMPTOTICALLY NONEXPANSIVE MAPPINGS

  • Yao, Yonghong;Liou, Yeong-Cheng;Kang, Shin-Min
    • Journal of applied mathematics & informatics
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    • v.28 no.1_2
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    • pp.75-86
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    • 2010
  • An iterative algorithm was been studied which can be viewed as an extension of the previously known algorithms for asymptotically nonexpansive mappings. Subsequently, we study the convergence problem of the proposed iterative algorithm for asymptotically nonexpansive mappings under some mild conditions in Banach spaces.

Design of an Efficient FTL Algorithm for Flash Memory Accesses Using Sector-level Mapping (섹터 매핑 기법을 적용한 효율적인 FTL 알고리듬 설계)

  • Yoon, Tae-Hyun;Kim, Kwang-Soo;Hwang, Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.12B
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    • pp.1418-1425
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    • 2009
  • This paper proposes a novel FTL (Flash Translation Layer) algorithm based on sector-level mapping to reduce the number of total erase operations in flash memory accesses. The proposed algorithm can reduce the number of erase operations by utilizing the sector-level mapping table when writing data at flash memory. Sector-level mapping technique reduces flash memory access time and extendsthe life time of the flash memory. In the algorithm, wear-leveling is implemented by selecting victim blocks having the minimal number of erase operations, when empty spaces for write are not available. To evaluate the performance of the proposed FTL algorithm, experiments were performed on several applications, such as MP3 players, MPEG players, web browsers and document editors. The proposed algorithm reduces the number of erase operations by 72.4% and 61.9%, when compared with well-known BAST and FAST algorithms, respectively.

Implementation of unsupervised clustering methods for measurement gases using artificial olfactory sensing system (인공 후각 센싱 시스템을 이용한 측정 가스의 Unsupervised clustering 방법의 구현)

  • 최지혁;함유경;최찬석;김정도;변형기
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.405-405
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    • 2000
  • We designed the artificial olfactory sensing system (Electronic Nose) using MOS type sensor array fur recognizing and analyzing odour. The response of individual sensors of sensor array, each processing a slightly different response towards the sample volatiles, can provide enough information to discriminate between sample odours. In this paper, we applied clustering algorithm for dimension reduction, such as linear projection mapping (PCA method), nonlinear mapping (Sammon mapping method) and the combination of PCA and Sammon mapping having a better discriminating ability. The odours used are VOC (Volatile chemical compound) and Toxic gases.

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A Study of FPGA Modul Algorithm consider the Power Consumption for Digital Technology (디지털 기술의 소모전력을 위한 FPGA 모듈 알고리즘에 관한연구)

  • Youn, Choong-Mo;Kim, Jae-Jin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.9
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    • pp.1851-1857
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    • 2009
  • In this paper, reuse module generation algorithm consider the power consumption for FPGA technology mapping is proposed. To proposed algorithm is RT library generating algorithm consider power consumption for reuse module using FPGA technology mapping. In the first, selected FPGA for power consumption calculation. Technology mapping process have minimum total power consumption consider LUT's constraint in selected FPGA. A circuit into device by selected proper modules of allocation result for power consumption constraint using data.

Energy-aware Virtual Resource Mapping Algorithm in Wireless Data Center

  • Luo, Juan;Fu, Shan;Wu, Di
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.8 no.3
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    • pp.819-837
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    • 2014
  • Data centers, which implement cloud service, have been faced up with quick growth of energy consumption and low efficiency of energy. 60GHz wireless communication technology, as a new option to data centers, can provide feasible approach to alleviate the problems. Aiming at energy optimization in 60GHz wireless data centers (WDCs), we investigate virtualization technology to assign virtual resources to minimum number of servers, and turn off other servers or adjust them to the state of low power. By comprehensive analysis of wireless data centers, we model virtual network and physical network in WDCs firstly, and propose Virtual Resource Mapping Packing Algorithm (VRMPA) to solve energy management problems. According to VRMPA, we adopt packing algorithm and sort physical resource only once, which improves efficiency of virtual resource allocation. Simulation results show that, under the condition of guaranteeing network load, VPMPA algorithm can achieve better virtual request acceptance rate and higher utilization rate of energy consumption.

Low Power CPLD Technology Mapping Algorithm for FLEX10K series (FLEX10K 계열에 대한 저전력 CPLD 기술 매핑 알고리즘)

  • 김재진;박남서;인치호;김희석
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.361-364
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    • 2002
  • In this paper, we consider the problem of CLB based CPLD technology mapping for power minimization in combinational circuit. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm for it. The main idea of our algorithm is to exploit the "cut enumeration" and "feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. However, for the consideration of both run time and memory space, only a fixed-number of solutions are selected and stored by our algorithm. To facilitate the selection process, a method that correctly calculates the estimated power consumption for each mapped sub-circuit is developed. The experimental results show that our approach is shown a decrease of 30.5% compared with DDMAP and that of 15.63% for TEMPLA in the Power consumption.

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Linear prediction and z-transform based CDF-mapping simulation algorithm of multivariate non-Gaussian fluctuating wind pressure

  • Jiang, Lei;Li, Chunxiang;Li, Jinhua
    • Wind and Structures
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    • v.31 no.6
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    • pp.549-560
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    • 2020
  • Methods for stochastic simulation of non-Gaussian wind pressure have increasingly addressed the efficiency and accuracy contents to offer an accurate description of the extreme value estimation of the long-span and high-rise structures. This paper presents a linear prediction and z-transform (LPZ) based Cumulative distribution function (CDF) mapping algorithm for the simulation of multivariate non-Gaussian fluctuating wind pressure. The new algorithm generates realizations of non-Gaussian with prescribed marginal probability distribution function (PDF) and prescribed spectral density function (PSD). The inverse linear prediction and z-transform function (ILPZ) is deduced. LPZ is improved and applied to non-Gaussian wind pressure simulation for the first time. The new algorithm is demonstrated to be efficient, flexible, and more accurate in comparison with the FFT-based method and Hermite polynomial model method in two examples for transverse softening and longitudinal hardening non-Gaussian wind pressures.

CONVERGENCE AND STABILITY OF ITERATIVE ALGORITHM OF SYSTEM OF GENERALIZED IMPLICIT VARIATIONAL-LIKE INCLUSION PROBLEMS USING (𝜃, 𝜑, 𝛾)-RELAXED COCOERCIVITY

  • Kim, Jong Kyu;Bhat, Mohd Iqbal;Shaf, Sumeera
    • Nonlinear Functional Analysis and Applications
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    • v.26 no.4
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    • pp.749-780
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    • 2021
  • In this paper, we give the notion of M(., .)-𝜂-proximal mapping for a nonconvex, proper, lower semicontinuous and subdifferentiable functional on Banach space and prove its existence and Lipschitz continuity. As an application, we introduce and investigate a new system of variational-like inclusions in Banach spaces. By means of M(., .)-𝜂-proximal mapping method, we give the existence of solution for the system of variational inclusions. Further, propose an iterative algorithm for finding the approximate solution of this class of variational inclusions. Furthermore, we discuss the convergence and stability analysis of the iterative algorithm. The results presented in this paper may be further expolited to solve some more important classes of problems in this direction.

Index block mapping for flash memory system (플래쉬 메모리 시스템을 위한 인덱스 블록 매핑)

  • Lee, Jung-Hoon
    • Journal of the Korea Society of Computer and Information
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    • v.15 no.8
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    • pp.23-30
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    • 2010
  • Flash memory is non-volatile and can retain data even after system is powered off. Besides, it has many other features such as fast access speed, low power consumption, attractive shock resistance, small size, and light-weight. As its price decreases and capacity increases, the flash memory is expected to be widely used in consumer electronics, embedded systems, and mobile devices. Flash storage systems generally adopt a software layer, called FTL. In this research, we proposed a new FTL mechanism for overcoming the major drawback of conventional block mapping algorithm. In addition to the block mapping table, a index block mapping table with a small size is used to indicate sector location. The proposed indexed block mapping algorithm by adding a small size. By the simulation result, the proposed FTL provides an enhanced speed than a conventional hybrid mapping algorithm by around 45% in average, and the requirement of mapping memory is also reduced by around 12%.