• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.1
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• pp.63-68
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• 2011

Many countries all over the world have been doing lunar exploration projects. Korea has also been doing basic research on lunar exploration. The development of communication systems for lunar exploration projects is one of the most important aspects of performing a successful lunar mission. In this paper, we design a DSP (Digital Signal Processor) prototype based on the requirement analysis of a communication link for lunar exploration and implement its core module considering the international standards for deep space communications to perform a basic research on baseband processor development. It is verified by comparing the bit error rate of the DSP prototype with that of a computer simulation.

• Journal of the Korea Convergence Society
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• v.7 no.5
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• pp.15-21
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• 2016

Recently the degree of integration of processor and developed rapidly. However, clock speed is not increased, a situation that increases the number of cores in the processor. In this paper, we analyze the performance of a typical Intel Xeon Phi of many core process used for the current operation accelerate. Utilizing the Quantum ESPRESSO, which was calculated using the FFTW library. By varying the number of ranks in MPI when running the benchmarks the performance Xeon Phi. The result shows a good performance in the handling of four job on one physical core. However, four or more to expand the number of MPI Rank is degraded. Through this convergence it was found to improve the performance of Quantum ESPRESSO. It is possible to check the hardware characteristics of the Xeon Phi.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.407-415
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• 2007

In parallel cluster computing systems, the efficiency of communication between computing nodes is one of important factors that decide overall system performance. Accordingly, many researchers have studied on high-performance inter-node communication. The recently launched multi-core processor, however. increases the importance of intra-node communication as well because the more the number of cores in a node, the more the number of parallel processes running in the same node. Though there have been studies on intra-node communications, these have limited considerations on the state-of-the-art systems. In this paper, we propose a Linux kernel module that minimizes the number of data copy by exploiting the memory mapping mechanism for high-performance intra-node communication. The proposed kernel module supports the Linux kernel version 2.6. The performance measurements over a multi-core system present that the proposed kernel module can achieve lower latency up to 62% and higher throughput up to 144% than an existing kernel module approach. In addition, the measurements reveal that the performance of intra-node communication can vary significantly based on whether the cores that run the communication processes are belong to the same processor package (i.e., sharing the L2 cache).

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.2
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• pp.728-741
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• 2015

Stereo vision has become an important technical issue in the field of 3D imaging, machine vision, robotics, image analysis, and so on. The depth map extraction from stereo video is a key technology of stereoscopic 3D video requiring stereo correspondence algorithms. This is the matching process of the similarity measure for each disparity value, followed by an aggregation and optimization step. Since it requires a lot of computational power, there are significant speed-performance advantages when exploiting parallel processing available on processors. In this situation, multi-core CPU may allow many parallel programming technologies to be realized in users computing devices. This paper proposes parallel implementations for calculating disparity map using a shared memory programming and exploiting the streaming SIMD extension technology. By doing so, we can take advantage both of the hardware and software features of multi-core processor. For the performance evaluation, we implemented a parallel SAD algorithm with OpenMP and SSE2. Their processing speeds are compared with non parallel version on stereoscopic streaming video. The experimental results show that both technologies have a significant effect on the performance and achieve great improvements on processing speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.44-55
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• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.73-76
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• 2014

With the increasing popularity of multi-core processors, they have been adopted even in embedded systems. Under this circumstance many multimedia applications can be parallelized on multi-core platforms because they usually require heavy computations and extensive memory accesses. This paper proposes an efficient thread-level parallel implementation for color space conversion on multi-core CPU. Thread-level parallelism has been becoming very useful parallel processing paradigm especially on shared memory computing systems. In this work, it is exploited by allocating different input pixels to each thread for concurrent loop executions. For the performance evaluation, this paper evaluate the performace improvements for color conversion on multi-core processors based on the processing speed comparison between its serial implementation and parallel ones. The results shows that thread-level parallel implementations show the overall similar ratios of performance improvements regardless of different multi-cores.

• The KIPS Transactions:PartB
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• v.18B no.4
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• pp.173-180
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• 2011

This paper shows an approach for real-time object segmentation on GPU (Graphics Processing Unit) using CUDA (Compute Unified Device Architecture). Recently, many applications that is monitoring system, motion analysis, object tracking or etc require real-time processing. It is not suitable for object segmentation to procedure real-time in CPU. NVIDIA provide CUDA platform for Parallel Processing for General Computation to upgrade limit of Hardware Graphic. In this paper, we use adaptive Gaussian Mixture Background Modeling in the step of object extraction and CCL(Connected Component Labeling) for classification. The speed of GPU and CPU is compared and evaluated with implementation in Core2 Quad processor with 2.4GHz.The GPU version achieved a speedup of 3x-4x over the CPU version.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.116-119
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• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.

• The Bulletin of The Korean Astronomical Society
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• v.44 no.2
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• pp.71.1-71.1
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• 2019

The solar magnetic field comes from the solar interior and is related to various phenomena on the Sun. To understand this process, many studies have been conducted to produce its evolution using a single flux rope. In this study, we are interested in the emergence of two flux ropes and their evolution, which takes longer than the emergence of a single flux rope. To construct it, we develop a flux emergence simulation by applying a parallel computing to reduce a computation time in a wider domain. The original simulation code had been written in Fortran 77. We modify it to a version of Fortran 90 with Message Passing Interface (MPI). The results of the original and new simulation are compared on the NEC SX-Aurora TSUBASA which is a vector engine processor. The parallelized version is faster than running on a single core and it shows a possibility to handle large amounts of calculation. Based on this model, we can construct a complex flux emergence system, such as an evolution of two magnetic flux ropes.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.1
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• pp.7-13
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• 2011

Matrix multiplication is a fundamental operation of linear algebra and arises in many areas of science and engineering. This paper introduces an efficient parallel matrix multiplication scheme on N ${\times}$ N mesh-connected SIMD array processor, called multiple hierarchical SIMD architecture (HMSA). The architectural characteristic of HMSA is the hierarchically structured control units which consist of a global control unit, N local control units configured diagonally, and $N^2$ processing elements (PEs) arranged in an N ${\times}$ N array. PEs are communicating through local buses connecting four adjacent neighbor PEs in mesh-torus networks and global buses running across the rows and columns called horizontal buses and vertical buses, respectively. This architecture enables HMSA to have the features of diagonally indexed concurrent broadcast and the accessibility to either rows (row control mode) or columns (column control mode) of 2D array PEs alternately. An algorithmic mapping method is used for performance evaluation by mapping matrix multiplication on the proposed architecture. The asymptotic time complexities of them are evaluated and the result shows that paralle matrix multiplication on HMSA can provide significant performance improvement.