• Natural Product Sciences
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• v.19 no.4
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• pp.324-328
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• 2013

Soy (Glycine max, family Leguminosae) contains isoflavones and saponins as main constituents. In our preliminary study, soybean ethanol extract (SE) ameliorated scopolamine-induced memory impairment in mice in the passive avoidance task. Therefore, to confirm its ameliorating effect for memory impairments, we measured its effect in scopolamine-induced memory-impaired mice in Morris water maze task. SE significantly prevented scopolamine-induced memory impairment in the Morris water maze task. SE also increased the swimming time within quadrant section of the platform on the day after the final training session test. SE protected the reduction of brain-derived neurotrophic factor (BDNF) expression and cAMP response element-binding protein (CREB) phosphorylation in the hippocampi of scopolamine-treated mice. However, SE did not inhibit acetylcholinesterase. To understand the possible role of soysaponins in memory impairments, we prepared soyasaponins-rich (butanol) fraction of soybean (SRF) and investigated its protective effect against in the passive avoidance and Morris water maze tasks. SRF ameliorated scopolamine-induced memory impairment in mice. The memory impairment-ameliorating effect of SRF was more effective than that of SE. Based on these findings, soybean may improve memory impairment by regulating CREB phosphorylation and BDNF expression.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.1
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• pp.99-107
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• 2001

In this paper, we implemented memory BIST circuit based on ION march algorithm, and the IEEE 1149.1 has been designed as main controlJer for embedded memory testing. The implemented memory BIST can be used for word-oriented memory since it adopts background data, this is avaliable for word-oriented memory. It is able to detect all stuck-at faults, transition faults, coupling faults, and address decoder faults in the word-oriented memory. Memory BIST and IEEE 1149.1 are described at RTL level in Verilog-HDL, and synthesized with the Synopsys. The synthesized circuits are fully velified using VerilogXL and memory cell generated by memory compiler.

• Journal of the Korea Society of Computer and Information
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• v.22 no.9
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• pp.1-8
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• 2017

In this paper, we propose a file system for flash memory which remedies shortcomings of existing flash memory file systems. Besides supporting large block size, the proposed file system reduces time in initializing file system significantly by adopting logical address comprised of erase block number and bitmap for pages in the block to find a page. The file system is suitable for embedded systems with limited main memory since it has small in-memory data structures. It also provides efficient management of obsolete blocks and free blocks, which contribute to the reduction of file update time. Finally the proposed file system can easily configure the maximum file size and file system size limits, which results in portability to emerging larger flash memories. By conducting performance evaluation studies, we show that the proposed file system can contribute to the performance improvement of embedded systems.

• Korean Journal of Cognitive Science
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• v.7 no.3
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• pp.61-80
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• 1996

Recent studies on emotion as memory,and effects of emotion on memory were reviewied. The main issues discussed were : memory of emotional events,relation between implicit memory and emotion, and the effect of emotion on autobigraphical memory. The theoretical possibility and implications that emotion is not stored as some lower level node information in semantic network but as some higher level and inclusive information were descussed.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.3
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• pp.177-184
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• 2017

High performance non-volatile memory system can mitigate the gap between main memory and storage. However, no single memory devices fulfill the requirements. Non-volatile Dual In-line Memory Module (NVDIMM) consisted of DRAMs and NAND Flashes has been proposed to achieve the performance and non-volatility simultaneously. When power outage occurs, data in DRAM is backed up into NAND Flash using a small-size external energy storage such as a supercapacitor. Backup and restore operations of NVDIMM do not cooperate with the operating system in the NVDIMM standard, thus there is room to optimize its operation. This paper analysis the operation of NVDIMM and proposes a method to reduce backup and restore time. Particularly, data compression is introduced to reduce the amount of data that to be backed up and restored. The simulation results show that the proposed method reduces up to 72.6% of backup and restore time.

• Korean Journal of Human Ecology
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• v.21 no.4
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• pp.705-714
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• 2012

This study investigated the relationships among emotion knowledge, negative emotionality, and autobiographical memory in a sample of 131 three- to five-year-old children attending day care center in seoul. The collected data were analyzed using simple regression and hierarchical multiple regression. The main results of this study were as follows. First, children's emotion knowledge exerted negative effects on their negative emotionality. Second, children's negative emotionality had a positive influence on their autobiographical memory. Finally, the effect of children's emotion knowledge on their autobiographical memory was partially mediated by their negative emotionality. These findings provide a preliminary evidence that children's emotion knowledge and negative emotionality may predict their autobiographical memory.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.3
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• pp.104-108
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• 2021

In order to improve performance in IoT, edge computing system, a memory is usually configured in a hierarchical structure. Based on the distance from CPU, the access speed slows down in the order of registers, cache memory, main memory, and storage. Similar to the change in performance, energy consumption also increases as the distance from the CPU increases. Therefore, it is important to develop a technique that places frequently used data to the upper memory as much as possible to improve performance and energy consumption. However, the technique should solve the problem of cache performance degradation caused by lack of spatial locality that occurs when the data access stride is large. This study proposes a technique to selectively place data with large data access stride to a software-controlled cache. By using the proposed technique, data spatial locality can be improved by reducing the data access interval, and consequently, the cache performance can be improved.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.175-178
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• 2004

This paper describes a new IP address lookup algorithm using a binary search on multiple balanced trees stored in one memory. The proposed scheme has 3 different tables; a range table, a main table, and multiple sub-tables. The range table includes $2^8$ entries of 22 bits wide. Each of the main table and sub-table entries is composed of fields for a prefix, a prefix length, the number of sub-table entries, a sub-table pointer, and a forwarding RAM pointer. Binary searches are performed in the main table and the multiple sub-tables in sequence. Address lookups in our proposed scheme are achieved by memory access times of 11 in average, 1 in minimum, and 24 in maximum using 267 Kbytes of memory for 38.000 prefixes. Hence the forwarding table of the proposed scheme is stored into L2 cache, and the address lookup algorithm is implemented in software running on general purpose processor. Since the proposed scheme only depends on the number of prefixes not the length of prefixes, it is easily scaled to IPv6.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1753-1765
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• 2000

As the areas of computer application are expanded, real-time application environments that must process as many transactions as possible within their deadlines, such as a stock transaction systems, ATM switching systems etc, have been increased recently. The reason why the conventional database systems can't process soft real-time applications is the lack of prediction and poor performance on processing transaction's deadline. If transactions want to access data stored at the secondary storage, they can not satisfy requirements of real-time applications because of the disk delay time. This paper designs a main-memory database prototype systems to be suitable to real-time applications and then this system can produce rapid results without disk i/o as all of the information are loaded in main memory database. In thesis proposed the improved techniques with respect to logging, checkpointing, and recovering in our environment. In order to improve the performance of the system, a) the frequency of log analysis and redo processing is reduced by the proposed redo technique at system failure, b) database consistency is maintained by improved fuzzy checkpointing. The performance model is proposed which consists of two parts. The first part evaluates log processing time for recovery and compares with other research activities. The second part examines checkpointing behavior.