• International Journal of Contents
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• v.3 no.1
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• pp.19-23
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• 2007

Recently, several main-memory index structures have been proposed to reduce the impact of secondary cache misses. In mainmemory storage systems, secondary cache misses have a substantial effect on the performance of index structures. However, recent studies still stiffer from secondary cache misses when visiting each level of index tree. In this paper, we propose a new index structure that minimizes the total amount of cache miss latency. The proposed index structure prefetched grandchildren of a current node. The basic structure of the proposed index structure is based on that of the CSB+-Tree, which uses the concept of a node group to increase fan-out. However, the insert algorithm of the proposed index structure significantly reduces the cost of a split. The superiority of our algorithm is shown through performance evaluation.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.117-123
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• 2016

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.741-749
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• 2014

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.33 no.2
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• pp.16-41
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• 2015

• Journal of KIISE:Databases
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• v.29 no.6
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• pp.464-476
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• 2002

Main-memory database systems which reside entire databases in main memory are suitable for high-performance real-time transaction processing. If two-phase locking(2PL) as concurrency control protocol is used for the transactions accessing main-memory databases, however, the possibility of lock conflict will be low but lock operations become relatively big overhead in total transaction processing time. In this paper, We designed a real-time static locking(RT-SL) protocol which minimizes lock operation overhead and reflects the priority of transactions and we implemented it on a main-memory real-time database system, Mr.RT. We also evaluate and compare its performance with the existing real-time locking protocols based on 2PL such as 2PL-PI and 2PL-HP. The extensive experiments reveal that our RT-SL outperforms the existing ones in most cases.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.9
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• pp.1867-1879
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• 1997

DREAM-S is a distributed main-memory database system for the real-time processing of shared operational datra in ATM switching systems. DREAM-S has a client-server architecture in which only the server has the diskstorage, and provides the T-Tree index structure for efficient accesses to the data. We propose a recovery technique for the T-Tree index structre in DREAM-S. Although main-memory database system offer efficient access performance, the database int he main-memory may be broken when system failure such as database transaction failure or power failure occurs. Therfore, a recovery technique that recovers the database (including index structures) is essential for fault tolerant ATM switching systems. Proposed recovery technique relieves the bottleneck of the server processors disk operations by maintaining the T-Tree index structure only in the main-memory. In addition, fast recovery is guaranteed even in large number of client systems since the T-Tree index structure(s) in each system can be recovered cncurrently.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• Journal of Korea Spatial Information System Society
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• v.8 no.2 s.17
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• pp.53-73
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• 2006

Recently, the need for Location-Based Services (LBS) has increased due to the development of mobile devices, such as PDAs, cellular phones and GPS. As a moving object database that stores and manages the positions of moving objects is the core technology of LBS, the scheme for maintaining the main memory DBMS to the server is necessary to store and process frequent reported positions of moving objects efficiently. However, previous works on a moving object database have studied mostly a disk based moving object index that is not guaranteed to work efficiently in the main memory DBMS because these indexes did not consider characteristics of the main memory. It is necessary to study the main memory index scheme for a moving object database. In this paper, we propose the main memory index scheme based on the R-tree for storing and processing positions of moving objects efficiently in the main memory DBMS. The proposed index scheme, which uses a growing node structure, prevents the splitting cost from increasing by delaying the node splitting when a node overflows. The proposed scheme also improves the search performance by using a MergeAndSplit policy for reducing overlaps between nodes and a LargeDomainNodeSplit policy for reducing a ratio of a domain size occupied by node's MBRs. Our experiments show that the proposed index scheme outperforms the existing index scheme on the maximum 30% for range queries.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1687-1696
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• 1996

Most of the main memory database systems use two-phase locking(2PL)for concurrency control. The 2PL method is preferred over other methods for concurrency control because of its simplicity and common usage. However, conventional concurrency control solution will function poorly when the data are memory resident. In this paper, we propose a new optimistic concurrency control protocol for a main memory database system. In our proposed protocol, transaction conflict information is used in validation phase to improve data conflict resolution decisions. Our experiments show that the proposed protocol performs better than 2PL in terms of throughput for main memory database system enshrinements.

• Journal of the Korea Society of Computer and Information
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• v.23 no.3
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• pp.1-8
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• 2018

In this paper, we propose a new page replacement policy using recency and frequency on hybrid main memory. The proposal has two features. First, when a page fault occurs in the main memory, the proposal allocates it to DRAM, regardless of operation types such as read or write. The page allocated by the page fault is likely to be high probability of re-reference in the near future. Our allocation can reduce the frequency of write operations in PCM. Second, if the write operations are frequently performed on pages of PCM, the pages are migrated from PCM to DRAM. Otherwise, the pages are maintained in PCM, to reduce the number of unnecessary page migrations from PCM. In our experiments, the proposal reduced the number of page migrations from PCM about 32.12% on average and reduced the number of write operations in PCM about 44.64% on average, compared to CLOCK-DWF. Moreover, the proposal reduced the energy consumption about 15.61%, and 3.04%, compared to other page replacement policies.