Journal of the Korea Society of Computer and Information (한국컴퓨터정보학회논문지)

Korean Society of Computer Information (한국컴퓨터정보학회)
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Recency and Frequency based Page Management on Hybrid Main Memory

  • Kim, Sungho (Dept. of Computer Engineering, Yeungnam University) ;
  • Kwak, Jong Wook (Dept. of Computer Engineering, Yeungnam University)
  • Received : 2017.11.30
  • Accepted : 2018.01.10
  • Published : 2018.03.30
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Abstract

In this paper, we propose a new page replacement policy using recency and frequency on hybrid main memory. The proposal has two features. First, when a page fault occurs in the main memory, the proposal allocates it to DRAM, regardless of operation types such as read or write. The page allocated by the page fault is likely to be high probability of re-reference in the near future. Our allocation can reduce the frequency of write operations in PCM. Second, if the write operations are frequently performed on pages of PCM, the pages are migrated from PCM to DRAM. Otherwise, the pages are maintained in PCM, to reduce the number of unnecessary page migrations from PCM. In our experiments, the proposal reduced the number of page migrations from PCM about 32.12% on average and reduced the number of write operations in PCM about 44.64% on average, compared to CLOCK-DWF. Moreover, the proposal reduced the energy consumption about 15.61%, and 3.04%, compared to other page replacement policies.

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References

  1. Dhiman. G, Ayoub. R, & Rosing. T, "PDRAM: a hybrid PRAM and DRAM main memory system," DAC'09, 46th ACM/IEEE, Design Automation Conference, pp. 664-669, July, 2009.
  2. International Roadmap Committee, "International technology roadmap for semiconductors," 2008.
  3. Zhou, P, Zhao. B, Yang. J, & Zhang. Y, "A durable and energy efficient main memory using phase change memory technology," ACM SIGARCH computer architecture news. Vol. 37, No. 3, pp. 14-23, June, 2009. https://doi.org/10.1145/1555815.1555759
  4. Qureshi. M. K, Srinivasan. V, & Rivers. J. A. "Scalable high performance main memory system using phase-change memory technology," ACM SIGARCH Computer Architecture News. Vol. 37, No. 3, pp. 24-33, 2009. https://doi.org/10.1145/1555815.1555760
  5. Qureshi. M. K, Karidis. J, Franceschini. M, Srinivasan. V, Lastras. L, & Abali. B, "Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling," Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, pp. 14-23, December, 2009.
  6. Ferreira. A. P, Zhou. M, Bock. S, Childers. B, Melhem. R, & Mosse. D, "Increasing PCM main memory lifetime," Proceedings of the conference on design, automation and test in Europe. European Design and Automation Association. pp. 914-919, March, 2010.
  7. Long, Linbo, et al. "A compiler assisted wear leveling for morphable PCM in embedded systems." Journal of Systems Architecture 71, pp. 32-43, 2016. https://doi.org/10.1016/j.sysarc.2016.06.007
  8. Khouzani, Hoda Aghaei, Fateme S. Hosseini, and Chengmo Yang. "Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main Memory." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 9, pp. 1458-1470, 2017. https://doi.org/10.1109/TCAD.2016.2615845
  9. Shirinzadeh, Saeideh, et al. "Endurance management for resistive Logic-In-Memory computing architectures." 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1092-1097, 2017.
  10. Yu. H, & Du. Y, "Increasing Endurance and Security of Phase-Change Memory with Multi-Way Wear-Leveling," IEEE Transactions on Computers, Vol. 63, No. 5, pp. 1157-1168, 2014. https://doi.org/10.1109/TC.2012.292
  11. Yu. H, & Du. Y, "Increasing Endurance and Security of Phase-Change Memory with Multi-Way Wear-Leveling," IEEE Transactions on Computers, Vol. 63, No. 5, pp. 1157-1168, 2014. https://doi.org/10.1109/TC.2012.292
  12. Xia. F, Jiang. D. J, Xiong. J, & Sun. N. H. "A survey of phase change memory systems," Journal of Computer Science and Technology, Vol. 30, No. 1, pp. 121-144, 2015. https://doi.org/10.1007/s11390-015-1509-2
  13. Mittal. S. A "survey of power management techniques for phase change memory," Memory, 1223, Vol. 41, No. 1, 2015.
  14. Jiang. S, & Zhang. X, "LIRS: an efficient low inter-reference recency set replacement policy to improve buffer cache performance," ACM SIGMETRICS Performance Evaluation Review, Vol. 30, No. 11, pp. 31-42, 2002.
  15. Megiddo. N, & Modha. D. S, "ARC: A Self-Tuning, Low Overhead Replacement Cache," FAST, Vol. 3, pp. 115-130, March, 2003.
  16. Bansal. S, & Modha. D. S. "CAR: Clock with Adaptive Replacement," FAST, Vol. 4, pp. 187-200, March, 2004.
  17. Jiang. S, Chen. F, & Zhang. X, "CLOCK-Pro: An Effective Improvement of the CLOCK Replacement," USENIX Annual Technical Conference, General Track, pp. 323-336, April, 2005.
  18. Lee. S, Bahn. H, & Noh. S. H, "Clock-dwf: A write-history-aware page replacement algorithm for hybrid pcm and dram memory architectures," IEEE Transactions on Computers, Vol. 63, No. 9, pp. 2187-2200, 2014. https://doi.org/10.1109/TC.2013.98
  19. Raoux. S, Burr. G. W, Breitwisch. M. J, Rettner. C. T, Chen. Y. C, Shelby. R. M, ... & Lam. C. H. "Phase-change random access memory: A scalable technology," IBM Journal of Research and Development, Vol. 52, No. 4.5, pp. 465-479, 2008. https://doi.org/10.1147/rd.524.0465
  20. Lee. B. C, Ipek. E, Mutlu. O, & Burger. D, "Architecting phase change memory as a scalable dram alternative," ACM SIGARCH Computer Architecture News. Vol. 37, No. 3, pp. 2-13. June, 2009. https://doi.org/10.1145/1555815.1555758
  21. Yang. B. D, Lee. J. E, Kim. J. S, Cho. J, Lee. S. Y, & Yu. B. G, "A low power phase-change random access memory using a data-comparison write scheme," 2007 IEEE International Symposium on Circuits and Systems, pp. 3014-3017, May, 2007.
  22. Cho. S, & Lee. H, "Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance," 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 347-357, December, 2009.
  23. Zhao. M, Shi. L, Yang. C, & Xue. C. J, "Leveling to the last mile: Near-zero-cost bit level wear leveling for PCM-based main memory," 2014 IEEE 32nd International Conference on Computer Design (ICCD), pp. 16-21, October, 2014.
  24. Corbato. F. J, "A paging experiment with the multics system (No. MAC-M-384)," MASSACHUSETTS INST OF TECH CAMBRIDGE PROJECT MAC. 1968.
  25. Binkert. N, Beckmann. B, Black. G, Reinhardt. S. K, Saidi. A, Basu. A, ... & Sen. R, "The gem5 simulator," ACM SIGARCH Computer Architecture News, Vol. 39, No. 22, pp. 1-7, 2011.
  26. Binkert. N. L, Dreslinski. R. G, Hsu. L. R, Lim. K. T, Saidi. A. G, & Reinhardt. S. K, "The M5 simulator: Modeling networked systems," IEEE Micro. Vol. 26, No. 4, pp. 52-60, 2006. https://doi.org/10.1109/MM.2006.82
  27. Martin. M. M, Sorin. D. J, Beckmann. B. M, Marty. M. R, Xu. M, Alameldeen. A. R, ... & Wood. D. A, " Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," ACM SIGARCH Computer Architecture News. Vol. 33, No. 4, pp. 92-99, 2005. https://doi.org/10.1145/1105734.1105747
  28. Henning. J. L, "SPEC CPU2006 benchmark descriptions," ACM SIGARCH Computer Architecture News. Vol. 34, No. 4, pp. 1-17, 2006. https://doi.org/10.1145/1186736.1186737
  29. Phansalkar. A, Joshi. A, & John. L. K, "Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite," ACM SIGARCH Computer Architecture News. Vol. 35, No. 2, pp. 412-423, 2007. https://doi.org/10.1145/1273440.1250713