• 한국멀티미디어학회논문지
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• 제2권4호
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• pp.367-377
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• 1999

최근 들어 신속한 트랜잭션 처리를 요구하는 데이터베이스 응용이 확대되고 있다. 트랜잭션 처리 시스템에서 높은 성능을 달성하기 위한 한가지 방법으로 데이터베이스를 디스크가 아닌 주기억장치에 모두 상주시키는 것이다. 반도체 메모리의 집적도가 증가하고 가격이 하락함에 따라 모든 데이터베이스를 주기억장치에 상주시켜 트랜잭션 처리율을 높이기 위한 연구가 이루어지고 있다. 본 논문에서는 주기억장치 데이터베이스를 기반으로 한 고성능 트랜잭션 처리 시스템을 구현하기 위하여 새로운 병행수행 제어 기법과 회복 기법 그리고 저장 구조를 제안하며, 트랜잭션의 처리량과 응답속도로 평가되는 트랜잭션 처리 시스템 성능의 개선을 목적으로 한다.

• Journal of Biosystems Engineering
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• 제26권2호
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• pp.177-188
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• 2001

This research was carried out to examine the optimum design conditions of a vertical small-scale milling machine where the rough rice is processed directly into the white rice in one pass. Effects of the main spindle speed, feed screw pitch and ceramic coating length of the roller on various milling characteristics such as white rice processing capacity, electric energy consumption, rice temperature increase, broken rice ratio, moisture reduction, outlet force and crack ratio increase were studied. The results are as follows. 1. The maximum white rice processing capacity and the lowest crack ratio increase, were obtained from a machine with specification: main spindle speed of 970rpm having a feed screw pitch of 19㎜. 2. The minimum electric energy consumption was obtained with the main spindle speeds of 900 and 970rpm respectively having a feed screw pitch of 19㎜. 3. The rice temperature was increased as the feed screw pitch decreased and the main spindle speed increased. 4. Broken rice ratio was relatively low with the range of 0.8∼1.3%. 5. Moisture content loss was with the range of 0.05∼0.4%. 6. The highest outlet force was 0.72kg$\_$f/ with 900rpm of the main spindle speed and 19㎜ of the feed screw pitch and the lowest outlet force was 0.18∼0.34kg$\_$f/ with 970rpm of the main spindle speed and 16㎜ of the feed screw pitch. 7. The optimum design conditions for the vertical small-scale milling machine were obtained at 970rpm of the main spindle speed, 19㎜ of the feed screw pitch and 20㎜ of the ceramics coating length.

• 제어로봇시스템학회논문지
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• 제3권6호
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• pp.626-631
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• 1997

This paper represents the design of a real-time image preprocessing system. The preprocessing system performs hardware-wise mask operations and thresholding operations at the speed of camera output single rate. The preprocessing system consists of the preprocessing board and the main processing board. The preprocessing board includes preprocessing unit that includes a $5\times5$ mask processor and LUT, and can perform mask and threshold operations in real-time. To achieve high-resolution image input data($20485\timesn$), the preprocessing board has a linescan camera interface. The main processing board includes the image processor unit and main processor unit. The image processor unit is equipped with TI's TMS320C32 DSP and can perform image processing algorithms at high speed. The main processor unit controls the operation of total system. The proposed system is faster than the conventional CPU based system.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2007년도 Proceedings of ISRS 2007
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• pp.544-547
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• 2007

Because data processing systems in recent years are more complicated, main function of the data processing is divided as several sub-functions which are implemented and verified in each subsystem of the data processing system. For the verification of data processing system, many interface tests among subsystems are required and also a lot of simulation systems are demanded. This paper proposes CTHS (Common Test Harness System) for satellite ground segment development which has all of functions for interface test of the data processing system in one PC. Main functions of the CTHS software are data interface, system log generation, and system information display. For the interface test of the data processing system, all of actions of the CTHS are executed by a pre-defined operation scenario which is written by purpose of the data processing system test.

• 만화애니메이션 연구
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• 통권40호
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• pp.243-260
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• 2015

안동 지역에서의 '원이엄마'를 모티브로 제작된 특수 영상 콘텐츠 애니메이션은 전통소재의 지역 콘텐츠의 발굴과 지적 재산권의 활용에 주요한 사례 연구로서의 가치를 가진다. 한국적 콘텐츠 개발의 과정에서의 사실 요소(FACTOR)와 픽션(FICTION)의 결합은 디자인 개발과 콘텐츠 연구에 중요한 부분으로서 작품 개발에 가장 큰 영향을 미치는 것이며, 전통 문화 캐릭터 개발 과정에서의 창의성 및 독창성과 함께 프리 프로덕션(Pre-Production)의 과정에서의 원화 기획의 핵심 역할이다. 한국적 콘텐츠는, 개발과정에서 한국적 캐릭터 개발과 함께 지속적으로 심도 있게 다루어 할 연구 과제이다. 여기에 각 캐릭터 디자인 구상과 기획에서의 과정의 고찰이 필요하며, 본 연구의 방향은 콘텐츠의 각 캐릭터 중 주요 주인공 캐릭터 개발의 과정을 통해 전통 문화 캐릭터가 개발되는 과정에 대한 이해와 사항들에 대한 디자인 결과물 연구이다. 의상과 고증을 통한 객관적 캐릭터 개발과정을 제시하여 전통문화 캐릭터 개발에 대한 이해과 방향을 제시하였다. 본론과 결론으로서는 전통적 문양 등의 개발 전체의 기획이 주인공 캐릭터에 어떤 형태로 적용되는지에 대한 과정과 도출, 그리고 세대 연령별에 따른 주인공 각 캐릭터에 대한 디자인이 드로잉 되었고, 안동시와 전통 캐릭터가 전통콘텐츠 창출에 어떤 의미를 가지는 것인지를 제시하였다.

• 한국의학물리학회:학술대회논문집
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• 한국의학물리학회 2002년도 Proceedings
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• pp.121-122
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• 2002

The main principle of radiation therapy is to deliver optimum dose to tumor to increase tumor cure probability while minimizing dose to critical normal structure to reduce complications. RTP system is required for proper dose plan in radiation therapy treatment. The main goal of this research is to develop dose model for photon, electron, and brachytherapy, and to display dose distribution on patient images with optimum process. The main items developed in this research includes: (l) user requirements and quality control; analysis of user requirement in RTP, networking between RTP and relevant equipment, quality control using phantom for clinical application (2) dose model in RTP; photon, electron, brachytherapy, modifying dose model (3) image processing and 3D visualization; 2D image processing, auto contouring, image reconstruction, 3D visualization (4) object modeling and graphic user interface; development of total software structure, step-by-step planning procedure, window design and user-interface. Our final product show strong capability for routine and advance RTP planning.

• 대한전자공학회논문지
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• 제27권6호
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• 한국정보처리학회논문지
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• 제7권6호
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• pp.1753-1765
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• 2000

As the areas of computer application are expanded, real-time application environments that must process as many transactions as possible within their deadlines, such as a stock transaction systems, ATM switching systems etc, have been increased recently. The reason why the conventional database systems can't process soft real-time applications is the lack of prediction and poor performance on processing transaction's deadline. If transactions want to access data stored at the secondary storage, they can not satisfy requirements of real-time applications because of the disk delay time. This paper designs a main-memory database prototype systems to be suitable to real-time applications and then this system can produce rapid results without disk i/o as all of the information are loaded in main memory database. In thesis proposed the improved techniques with respect to logging, checkpointing, and recovering in our environment. In order to improve the performance of the system, a) the frequency of log analysis and redo processing is reduced by the proposed redo technique at system failure, b) database consistency is maintained by improved fuzzy checkpointing. The performance model is proposed which consists of two parts. The first part evaluates log processing time for recovery and compares with other research activities. The second part examines checkpointing behavior.

• 한국통신학회논문지
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• 제26권11A호
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• pp.1963-1970
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• 2001

It is essential design process to analyze processing method and set out top level HW configuration using main parameters before implementation of the SAR processor. This paper identifies the impact of the I/O and algorithm structure upon the parallel processing to be assessed and suggests the practical mapping method fur parallel processing to the SAR data. Also, simulation is performed to the E-SAR processor to examine the usefulness of the method, and the results are analyzed and discussed.

• 제어로봇시스템학회논문지
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• 제10권2호
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• pp.178-184
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• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.